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| user? manual printed in japan document no. u12013ej3v2ud00 (3rd edition) date published february 2003 n cp (k) 1997, 2003 pd780058, 780058y subseries 8-bit single-chip microcontrollers pd780053 pd780053y pd780054 pd780054y pd780055 pd780055y pd780056 pd780056y pd780058 pd780058by pd780058b pd78f0058y pd78f0058 pd780053y(a) pd780053(a) pd780054y(a) pd780054(a) pd780055y(a) pd780055(a) pd780056y(a) pd780056(a) pd780058by(a) pd780058b(a)
2 user's manual u12013ej3v2ud [memo] 3 user's manual u12013ej3v2ud notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip, eeprom, and iebus are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. tron stands for the realtime operating system nucleus. itron is an abbreviation of industrial tron. 4 user's manual u12013ej3v2ud purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of january, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 5 user's manual u12013ej3v2ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v?lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: 6 user's manual u12013ej3v2ud major revisions in this edition (1/2) page description throughout deletion of following product pd780058y addition of following products pd780058b, 780058by, 780053(a), 780053y(a), 780054(a), 780054y(a), 780055(a), 780055y(a), 780056(a), 780056y(a), 780058b(a), 780058by(a) deletion of following packages 80-pin plastic qfp (gc-3b9 type) 80-pin plastic tqfp (gk-be9 type) addition of following package 80-pin plastic tqfp (gk-9eu type) pp. 31, 32, 38, 39 1.1 features, 1.7 outline of functions change of operating voltage range of a/d and d/a converters of pd780058 and 78f0058 change of supply voltage of pd78f0058 p. 40 addition of 1.9 differences between standard model and (a) model pp. 41, 42, 48, 49 2.1 features, 2.7 outline of functions change of operating voltage range of a/d and d/a converters of pd78f0058y change of supply voltage of pd78f0058y p. 50 addition of 2.9 differences between standard model and (a) model p. 60 change of processing when a/d converter is not used in 3.2.11 av ref0 pp. 62, 63 change of recommended connection of unused pins and connection of p60 to p63, av ref1 , and v pp pins in table 3-1 pin i/o circuit types p. 75 change of processing when a/d converter is not used in 4.2.11 av ref0 pp. 77, 78 change of recommended connection of unused pins and connection of p60 to p63, av ref1 , and v pp pins in table 4-1 pin i/o circuit types p. 132 modification of note 2 in 6.2.8 port 6 p. 149 addition of note on feedback resistor to figure 7-3 processor clock control register format p. 167 addition of table 8-5 intp1/ti01 pin valid edge and cr00 capture trigger valid edge p. 168 addition of table 8-6 intp0/ti00 pin valid edge and cr01 capture trigger valid edge p. 177 correction of note on valid edge of intp0/ti00/p00 and intp1/ti01/p01 pin in figure 8-8 format of external interrupt mode register 0 p. 185 addition of figure 8-17 configuration of ppg output addition of figure 8-18 ppg output operation timing pp. 201 to 204 8.5 16-bit timer/event counter operating cautions addition of description on ti01/p01/intp1 to (5) valid edge setting addition of (c) one-shot pulse output function to (6) re-trigger of one-shot pulse addition of (8) conflict operation addition of (9) timer operation addition of (10) capture operation addition of (11) compare operation addition of (12) edge detection p. 235 modification of note on changing count clock in figure 10-2 timer clock select register 2 format p. 242 modification of note on changing count clock in figure 11-2 timer clock select register 2 format p. 252 addition of note on rewriting tcl2 in figure 13-2 format of timer clock select register 2 7 user's manual u12013ej3v2ud major revisions in this edition (2/2) page description p. 263 modification of figure 14-5 a/d converter basic operation addition of table 14-2 a/d conversion sampling time and a/d converter start delay time pp. 267, 268 addition of 14.5 how to read a/d converter characteristics table pp. 269, 270, 272, 273 14.6 a/d converter cautions change of description in (1) power consumption in standby mode addition of (3) conflict operations addition of (6) input impedance of ani0 to ani7 pins addition of (10) timing at which a/d conversion result is undefined addition of (11) notes on board design addition of (12) av ref0 pin addition of (13) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance p. 280 addition of description of processing when d/a converter is not used in 15.5 d/a converter cautions (3) av ref1 pin p. 379 addition of 17.4.7 restrictions in i 2 c bus mode 2 p. 468 addition of 19.4.5 restrictions in uart mode 2 p. 477 addition of caution when interrupt is acknowledged to figure 21-2 interrupt request flag register format p. 483 addition of description on ti01/p01/intp1 pin to figure 21-5 format of external interrupt mode register 0 p. 525 addition of caution to 25.1 rom correction function p. 535 modification of table 26-1 differences between pd78f0058, 78f0058y and mask rom versions pp. 538 to 549 total revision of description on flash memory programming as 26.3 flash memory characteristics pp. 567 to 596 addition of chapter 28 electrical specifications (mask rom version) pp. 597 to 626 addition of chapter 29 electrical specifications (flash memory version) pp. 627 to 657 addition of chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) pp. 658, 659 addition of chapter 31 characteristics curves (reference values) pp. 660, 661 addition of chapter 32 package drawings pp. 662 to 665 addition of chapter 33 recommended soldering conditions pp. 666, 667 correction of appendix a differences between pd78054, 78058f, and 780058 subseries pp. 668 to 684 total revision of appendix b development tools transfer of description of embedded software to appendix b development tools the mark shows major revised points. 8 user's manual u12013ej3v2ud preface readers this manual has been prepared for user engineers who wish to understand the functions of the pd780058 and 780058y subseries and design and develop its application systems and programs. this manual is intended for the products in the following subseries. pd780058 subseries pd780053, 780054, 780055, 780056, 780058, 780058b, 78f0058, 780053(a), 780054(a), 780055(a), 780056(a), 780058b(a) pd780058y subseries pd780053y, 780054y, 780055y, 780056y, 780058by, 78f0058y, 780053y(a), 780054y(a), 780055y(a), 780056y(a), 780058by(a) these products are collectively referred to as the pd780058, 780058y subseries in this manual. purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the pd780058, 780058y subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). pd780058, 780058y 78k/0 series subseries user? manual user? manual instructions (this manual) pin functions cpu functions internal block functions instruction set interrupts explanation of each instruction other on-chip peripheral functions electrical specifications 9 user's manual u12013ej3v2ud how to read this manual it is assumed that readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. when using this manual as the manual for the pd780053(a), 780054(a), 780055(a), 780056(a), 780058b(a), 780053y(a), 780054y(a), 780055y(a), 780056y(a), and 780058by(a), the only difference between these products and the pd780053, 780054, 780055, 780056, 780058b, 780053y, 780054y, 780055y, 780056y, and 780058by is the quality grade (see 1.9 differences between standard model and (a) model , and 2.9 differences between standard model and (a) model ). the correspondence between the standard model and (a) model is as follows in chapter 6 port functions to chapter 27 instruc- tion set outline . pd780053 pd780053(a) pd780053y pd780053y(a) pd780054 pd780054(a) pd780054y pd780054y(a) pd780055 pd780055(a) pd780055y pd780055y(a) pd780056 pd780056(a) pd780056y pd780056y(a) pd780058b pd780058b(a) pd780058by pd780058by(a) to gain a general understanding the functions: read this manual in the order of the contents. to know the pd780058 and 780058y subseries instruction functions in detail: refer to the 78k/0 series instructions user? manual (u12326e) how to interpret the register format: for a bit number enclosed in angle brackets (<>), the bit name is defined as a reserved word in the ra78k 0, and defined in the header file named sfrbit.h in the cc78k0. to learn the function of a register whose register name is known: refer to appendix c register index . to see application examples of each function of the pd780058, 780058y subseries: refer to 78k/0 series basics (iii) application note (u10182e) separately available. to understand the electrical specifications of the pd780058, 780058y subseries: see chapter 28 electrical specifications (mask rom ver- sion) , chapter 29 electrical specifications (flash memory version) , chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) . caution examples in this manual employ the ?tandard?quality grade for general electronics. when using examples in this manual for the ?pecial?quality grade, review the quality grade of each part and/or circuit actually used. 10 user's manual u12013ej3v2ud chapter organization : this manual divides the descriptions for the pd780058 and 780058y subseries into different chapters as shown below. read only the chapters related to the device being used. chapter pd780058 pd780058y subseries subseries chapter 1 outline ( pd780058 subseries) chapter 2 outline ( pd780058y subseries) chapter 3 pin functions ( pd780058 subseries) chapter 4 pin functions ( pd780058y subseries) chapter 5 cpu architecture ? chapter 6 port functions ? chapter 7 clock generator ? chapter 8 16-bit timer/event counter ? chapter 9 8-bit timer/event counter ? chapter 10 watch timer ? chapter 11 watchdog timer ? chapter 12 clock output controller ? chapter 13 buzzer output controller ? chapter 14 a/d converter ? chapter 15 d/a converter ? chapter 16 serial interface channel 0 ( pd780058 subseries) chapter 17 serial interface channel 0 ( pd780058y subseries) chapter 18 serial interface channel 1 ? chapter 19 serial interface channel 2 ? chapter 20 real-time output port ? chapter 21 interrupt and test functions ? chapter 22 external device expansion function ? chapter 23 standby function ? chapter 24 reset function ? chapter 25 rom correction ? chapter 26 pd78f0058, pd78f0058y ? chapter 27 outline of instruction set ? chapter 28 electrical specifications (mask rom version) ? chapter 29 electrical specifications (flash memory version) ? chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) ? chapter 31 characteristics curves (reference values) ? chapter 32 package drawings ? chapter 33 recommended soldering conditions ? 11 user's manual u12013ej3v2ud differences between pd780058 and pd780058y subseries: the pd780058 and pd780058y subseries differ in the following functions of serial interface channel 0. modes of serial interface channel 0 pd780058 pd780058y subseries subseries 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi (serial bus interface) mode i 2 c (inter ic) bus mode : supported ? not supported legend data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin or signal name) note : footnote for item marked with note in the text. caution : information requiring particular attention remark : supplementary information numeral representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780058, 780058y subseries user's manual this manual 78k/0 series instruction user's manual u12326e 78k/0 series basics (iii) application note u10182e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 user's manual u12013ej3v2ud documents related to software development tools (user? manuals) document name document no. ra78k0 assember package operation u14445e language u14446e structure assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k series system simulator ver. 2.30 or later operation (windows tm based) u15373e external part user open interface specification u15802e id78k series integrated debugger ver. 2.30 or later operation (windows based) u15185e rx78k0 real-time os fundamentals u11537e installation u11536e project manager ver. 3.12 or later (windows based) u14610e documents related to hardware development tools (user? manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-780308-ns-em1 emulation board u13304e ie-78001-r-a in-circuit emulator u14142e ie-780308-r-em emulation board u11362e documents related to flash memory writing document name document no. pg-fp3 flash memory programmer user? manual u13502e pg-fp4 flash memory programmer user? manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 13 user's manual u12013ej3v2ud contents chapter 1 outline ( pd780058 subseries) ......................................................................... 31 1.1 features ............................................................................................................................... .31 1.2 applications ......................................................................................................................... 32 1.3 ordering information .......................................................................................................... 32 1.4 pin configuration (top view) ............................................................................................. 33 1.5 78k/0 series lineup ............................................................................................................ 35 1.6 block diagram ..................................................................................................................... 37 1.7 outline of function ............................................................................................................. 38 1.8 mask options ....................................................................................................................... 40 1.9 differences between standard model and (a) model .................................................... 40 chapter 2 outline ( pd780058y subseries) ....................................................................... 41 2.1 features ............................................................................................................................... .41 2.2 applications ......................................................................................................................... 42 2.3 ordering information .......................................................................................................... 42 2.4 pin configuration (top view) ............................................................................................. 43 2.5 78k/0 series lineup ............................................................................................................ 45 2.6 block diagram ..................................................................................................................... 47 2.7 outline of functions ........................................................................................................... 48 2.8 mask options ....................................................................................................................... 50 2.9 differences between standard model and (a) model .................................................... 50 chapter 3 pin functions ( pd780058 subseries) ............................................................. 51 3.1 pin function list ................................................................................................................. 51 3.2 description of pin functions ............................................................................................ 55 3.2.1 p00 to p05, p07 (port 0) ........................................................................................................ 55 3.2.2 p10 to p17 (port 1) ................................................................................................................. 55 3.2.3 p20 to p27 (port 2) ................................................................................................................. 56 3.2.4 p30 to p37 (port 3) ................................................................................................................. 57 3.2.5 p40 to p47 (port 4) ................................................................................................................. 57 3.2.6 p50 to p57 (port 5) ................................................................................................................. 58 3.2.7 p60 to p67 (port 6) ................................................................................................................. 58 3.2.8 p70 to p72 (port 7) ................................................................................................................. 59 3.2.9 p120 to p127 (port 12) ........................................................................................................... 59 3.2.10 p130 and p131 (port 13) ........................................................................................................ 60 3.2.11 av ref0 ............................................................................................................................... ....... 60 3.2.12 av ref1 ............................................................................................................................... ....... 60 3.2.13 av ss ............................................................................................................................... .......... 60 3.2.14 reset ............................................................................................................................... ...... 60 3.2.15 x1 and x2 ............................................................................................................................... .60 3.2.16 xt1 and xt2 ........................................................................................................................... 60 3.2.17 v dd0 , v dd1 ............................................................................................................................... .60 3.2.18 v ss0 , v ss1 ............................................................................................................................... .. 61 3.2.19 v pp (flash memory version only) ........................................................................................... 61 3.2.20 ic (mask rom version only) .................................................................................................. 61 3.3 i/o circuits and recommended connection of unused pins ....................................... 62 14 user's manual u12013ej3v2ud chapter 4 pin functions ( pd780058y subseries) .......................................................... 66 4.1 pin function list ................................................................................................................. 66 4.2 description of pin functions ............................................................................................ 70 4.2.1 p00 to p05, p07 (port 0) ........................................................................................................ 70 4.2.2 p10 to p17 (port 1) ................................................................................................................. 71 4.2.3 p20 to p27 (port 2) ................................................................................................................. 71 4.2.4 p30 to p37 (port 3) ................................................................................................................. 72 4.2.5 p40 to p47 (port 4) ................................................................................................................. 73 4.2.6 p50 to p57 (port 5) ................................................................................................................. 73 4.2.7 p60 to p67 (port 6) ................................................................................................................. 73 4.2.8 p70 to p72 (port 7) ................................................................................................................. 74 4.2.9 p120 to p127 (port 12) ........................................................................................................... 74 4.2.10 p130 and p131 (port 13) ....................................................................................................... 75 4.2.11 av ref0 ............................................................................................................................... ....... 75 4.2.12 av ref1 ............................................................................................................................... ....... 75 4.2.13 av ss ............................................................................................................................... .......... 75 4.2.14 reset ............................................................................................................................... ...... 75 4.2.15 x1 and x2 ............................................................................................................................... .75 4.2.16 xt1 and xt2 ........................................................................................................................... 75 4.2.17 v dd0 , v dd1 ............................................................................................................................... .75 4.2.18 v ss0 , v ss1 ............................................................................................................................... .. 76 4.2.19 v pp (flash memory version only) ........................................................................................... 76 4.2.20 ic (mask rom version only) .................................................................................................. 76 4.3 i/o circuits and recommended connection of unused pins ....................................... 77 chapter 5 cpu architecture ................................................................................................. 81 5.1 memory spaces ................................................................................................................... 81 5.1.1 internal program memory space .............................................................................................. 87 5.1.2 internal data memory space .................................................................................................... 89 5.1.3 special function register (sfr) area .................................................................................... 89 5.1.4 external memory space ........................................................................................................... 89 5.1.5 data memory addressing ......................................................................................................... 89 5.2 processor registers ........................................................................................................... 96 5.2.1 control registers ....................................................................................................................... 96 5.2.2 general registers ...................................................................................................................... 99 5.2.3 special-function registers (sfrs) ......................................................................................... 100 5.3 instruction address addressing ....................................................................................... 104 5.3.1 relative addressing .................................................................................................................. 104 5.3.2 immediate addressing .............................................................................................................. 105 5.3.3 table indirect addressing ......................................................................................................... 106 5.3.4 register addressing ................................................................................................................. 107 5.4 operand address addressing ........................................................................................... 108 5.4.1 implied addressing ................................................................................................................... 108 5.4.2 register addressing ................................................................................................................. 109 5.4.3 direct addressing ..................................................................................................................... 110 5.4.4 short direct addressing ............................................................................................................ 111 5.4.5 special-function register (sfr) addressing .......................................................................... 113 5.4.6 register indirect addressing .................................................................................................... 114 5.4.7 based addressing ..................................................................................................................... 115 15 user's manual u12013ej3v2ud 5.4.8 based indexed addressing ....................................................................................................... 116 5.4.9 stack addressing ...................................................................................................................... 116 chapter 6 port functions ...................................................................................................... 117 6.1 port functions ..................................................................................................................... 117 6.2 port configuration .............................................................................................................. 122 6.2.1 port 0 ............................................................................................................................... ........ 122 6.2.2 port 1 ............................................................................................................................... ........ 124 6.2.3 port 2 ( pd780058 subseries) .............................................................................................. 125 6.2.4 port 2 ( pd780058y subseries) ............................................................................................ 127 6.2.5 port 3 ............................................................................................................................... ........ 129 6.2.6 port 4 ............................................................................................................................... ........ 130 6.2.7 port 5 ............................................................................................................................... ........ 131 6.2.8 port 6 ............................................................................................................................... ........ 132 6.2.9 port 7 ............................................................................................................................... ........ 134 6.2.10 port 12 ............................................................................................................................... ...... 136 6.2.11 port 13 ............................................................................................................................... ...... 137 6.3 port function control registers ....................................................................................... 138 6.4 port operations ................................................................................................................... 144 6.4.1 writing to i/o port ..................................................................................................................... 144 6.4.2 reading from i/o port .............................................................................................................. 144 6.4.3 operations on i/o port ............................................................................................................. 144 6.5 selection of mask option ................................................................................................... 145 chapter 7 clock generator .................................................................................................. 146 7.1 clock generator functions ................................................................................................ 146 7.2 clock generator configuration ......................................................................................... 146 7.3 clock generator control registers .................................................................................. 148 7.4 system clock oscillator ..................................................................................................... 152 7.4.1 main system clock oscillator .................................................................................................... 152 7.4.2 subsystem clock oscillator ....................................................................................................... 153 7.4.3 example of resonator with bad connection ............................................................................. 154 7.4.4 divider ............................................................................................................................... ........ 155 7.4.5 when not using subsystem clock ............................................................................................ 155 7.5 clock generator operations .............................................................................................. 156 7.5.1 main system clock operations .................................................................................................. 157 7.5.2 subsystem clock operations .................................................................................................... 158 7.6 changing system clock and cpu clock settings ......................................................... 159 7.6.1 time required for switchover between system clock and cpu clock ..................................... 159 7.6.2 system clock and cpu clock switching procedure ................................................................. 161 chapter 8 16-bit timer/event counter ............................................................................... 162 8.1 16-bit timer/event counter functions ............................................................................. 162 8.2 16-bit timer/event counter configuration ...................................................................... 164 8.3 16-bit timer/event counter control registers ............................................................... 169 8.4 16-bit timer/event counter operations ........................................................................... 179 8.4.1 interval timer operations .......................................................................................................... 179 8.4.2 pwm output operations ............................................................................................................ 181 8.4.3 ppg output operations ............................................................................................................. 184 8.4.4 pulse width measurement operations ..................................................................................... 186 16 user's manual u12013ej3v2ud 8.4.5 external event counter operation ............................................................................................. 193 8.4.6 square-wave output operation ................................................................................................. 195 8.4.7 one-shot pulse output operation ............................................................................................. 197 8.5 16-bit timer/event counter operating cautions ............................................................ 201 chapter 9 8-bit timer/event counter ................................................................................. 205 9.1 8-bit timer/event counter functions ............................................................................... 205 9.1.1 8-bit timer/event counter mode ................................................................................................ 205 9.1.2 16-bit timer/event counter mode .............................................................................................. 208 9.2 8-bit timer/event counter configuration ........................................................................ 210 9.3 8-bit timer/event counter control registers .................................................................. 214 9.4 operations of 8-bit timer/event counters 1 and 2 ........................................................ 219 9.4.1 8-bit timer/event counter mode ................................................................................................ 219 9.4.2 16-bit timer/event counter mode .............................................................................................. 225 9.5 cautions on 8-bit timer/event counters 1 and 2 ........................................................... 230 chapter 10 watch timer ............................................................................................................ 232 10.1 watch timer functions ..................................................................................................... 232 10.2 watch timer configuration .............................................................................................. 233 10.3 watch timer control registers ........................................................................................ 233 10.4 watch timer operations ................................................................................................... 237 10.4.1 watch timer operation ............................................................................................................ 237 10.4.2 interval timer operation .......................................................................................................... 237 chapter 11 watchdog timer ................................................................................................... 238 11.1 watchdog timer functions .............................................................................................. 238 11.2 watchdog timer configuration ........................................................................................ 240 11.3 watchdog timer control registers ................................................................................. 241 11.4 watchdog timer operations ............................................................................................ 244 11.4.1 watchdog timer operation ...................................................................................................... 244 11.4.2 interval timer operation .......................................................................................................... 245 chapter 12 clock output controller ............................................................................. 246 12.1 clock output controller functions ................................................................................ 246 12.2 clock output controller configuration .......................................................................... 247 12.3 clock output function control registers ..................................................................... 247 chapter 13 buzzer output controller ........................................................................... 250 13.1 buzzer output controller functions .............................................................................. 250 13.2 buzzer output controller configuration ........................................................................ 250 13.3 buzzer output function control registers ................................................................... 251 chapter 14 a/d converter ...................................................................................................... 254 14.1 a/d converter functions ................................................................................................. 254 14.2 a/d converter configuration ........................................................................................... 254 14.3 a/d converter control registers .................................................................................... 258 14.4 a/d converter operations ................................................................................................ 262 14.4.1 basic operations of a/d converter ......................................................................................... 262 14.4.2 input voltage and conversion results ..................................................................................... 264 14.4.3 a/d converter operating mode ............................................................................................... 265 17 user's manual u12013ej3v2ud 14.5 how to read the a/d converter characteristics table ................................................ 267 14.6 a/d converter cautions ................................................................................................... 269 chapter 15 d/a converter ...................................................................................................... 275 15.1 d/a converter functions ................................................................................................. 275 15.2 d/a converter configuration ........................................................................................... 276 15.3 d/a converter control registers .................................................................................... 278 15.4 d/a converter operations ................................................................................................ 279 15.5 d/a converter cautions ................................................................................................... 280 chapter 16 serial interface channel 0 ( pd780058 subseries) .............................. 281 16.1 functions of serial interface channel 0 ........................................................................ 282 16.2 configuration of serial interface channel 0 ................................................................. 284 16.3 control registers of serial interface channel 0 ........................................................... 288 16.4 operations of serial interface channel 0 ...................................................................... 295 16.4.1 operation stop mode .............................................................................................................. 295 16.4.2 3-wire serial i/o mode operation ........................................................................................... 296 16.4.3 sbi mode operation ............................................................................................................... 301 16.4.4 2-wire serial i/o mode operation ........................................................................................... 327 16.4.5 sck0/p27 pin output manipulation ....................................................................................... 332 chapter 17 serial interface channel 0 ( pd780058y subseries) ........................... 333 17.1 functions of serial interface channel 0 ........................................................................ 334 17.2 configuration of serial interface channel 0 ................................................................. 336 17.3 control registers of serial interface channel 0 ........................................................... 340 17.4 operations of serial interface channel 0 ...................................................................... 347 17.4.1 operation stop mode .............................................................................................................. 347 17.4.2 3-wire serial i/o mode operation ........................................................................................... 348 17.4.3 2-wire serial i/o mode operation ........................................................................................... 352 17.4.4 i 2 c bus mode operation ......................................................................................................... 357 17.4.5 cautions on use of i 2 c bus mode ......................................................................................... 374 17.4.6 restrictions in i 2 c bus mode 1 .............................................................................................. 377 17.4.7 restrictions in i 2 c bus mode 2 .............................................................................................. 379 17.4.8 sck0/scl/p27 pin output manipulation ............................................................................... 380 chapter 18 serial interface channel 1 ........................................................................... 382 18.1 functions of serial interface channel 1 ........................................................................ 382 18.2 configuration of serial interface channel 1 ................................................................. 383 18.3 control registers of serial interface channel 1 ........................................................... 386 18.4 operations of serial interface channel 1 ...................................................................... 394 18.4.1 operation stop mode .............................................................................................................. 394 18.4.2 3-wire serial i/o mode operation ........................................................................................... 395 18.4.3 3-wire serial i/o mode operation with automatic transmit/receive function ......................... 398 chapter 19 serial interface channel 2 ........................................................................... 427 19.1 functions of serial interface channel 2 ........................................................................ 427 19.2 configuration of serial interface channel 2 ................................................................. 428 19.3 control registers of serial interface channel 2 ........................................................... 432 19.4 operation of serial interface channel 2 ........................................................................ 442 19.4.1 operation stop mode .............................................................................................................. 442 18 user's manual u12013ej3v2ud 19.4.2 asynchronous serial interface (uart) mode (with time-division transfer function) ............ 444 19.4.3 3-wire serial i/o mode ............................................................................................................ 458 19.4.4 restrictions in uart mode 1 ................................................................................................ 465 19.4.5 restrictions in uart mode 2 ................................................................................................ 468 chapter 20 real-time output port ..................................................................................... 469 20.1 real-time output port functions ................................................................................... 469 20.2 real-time output port configuration ............................................................................ 470 20.3 real-time output port control registers ...................................................................... 472 chapter 21 interrupt and test functions ...................................................................... 474 21.1 interrupt function types .................................................................................................. 474 21.2 interrupt sources and configuration ............................................................................. 475 21.3 interrupt function control registers ............................................................................. 479 21.4 interrupt servicing operations ....................................................................................... 488 21.4.1 non-maskable interrupt request acknowledgment operation ............................................... 488 21.4.2 maskable interrupt request acknowledgment operation ....................................................... 491 21.4.3 software interrupt request acknowledgment operation ........................................................ 494 21.4.4 multiple interrupt servicing ..................................................................................................... 494 21.4.5 interrupt request pending ....................................................................................................... 497 21.5 test function ..................................................................................................................... 498 21.5.1 registers controlling test function ......................................................................................... 498 21.5.2 test input signal acknowledgment operation ........................................................................ 500 chapter 22 external device expansion function ....................................................... 501 22.1 external device expansion function ............................................................................. 501 22.2 external device expansion function control register ............................................... 505 22.3 external device expansion function timing ................................................................ 507 22.4 example of connection with memory ............................................................................ 512 chapter 23 standby function .............................................................................................. 513 23.1 standby function and configuration ............................................................................. 513 23.1.1 standby function ..................................................................................................................... 513 23.1.2 standby function control register ........................................................................................... 514 23.2 standby function operations ......................................................................................... 515 23.2.1 halt mode ............................................................................................................................. 51 5 23.2.2 stop mode ............................................................................................................................ 518 chapter 24 reset function .................................................................................................... 521 24.1 reset function .................................................................................................................. 521 chapter 25 rom correction ................................................................................................. 525 25.1 rom correction function ................................................................................................ 525 25.2 rom correction configuration ....................................................................................... 525 25.3 rom correction control registers ................................................................................. 527 25.4 rom correction application ............................................................................................ 528 25.5 rom correction usage example .................................................................................... 531 25.6 program execution flow .................................................................................................. 532 25.7 rom correction cautions ................................................................................................ 534 19 user's manual u12013ej3v2ud chapter 26 pd78f0058, 78f0058y ............................................................................................ 535 26.1 internal memory size switching register ..................................................................... 536 26.2 internal expansion ram size switching register ....................................................... 537 26.3 flash memory characteristics ........................................................................................ 538 26.3.1 programming environment ..................................................................................................... 538 26.3.2 communication mode ............................................................................................................ 539 26.3.3 on-board pin processing ........................................................................................................ 543 26.3.4 connection of adapter for flash writing ................................................................................. 546 chapter 27 instruction set overview ............................................................................... 552 27.1 conventions used in operation list .............................................................................. 553 27.1.1 operand identifiers and description methods ....................................................................... 553 27.1.2 description of operation column ............................................................................................ 554 27.1.3 description of flag operation column ..................................................................................... 554 27.2 operation list .................................................................................................................... 555 27.3 instructions listed by addressing type ........................................................................ 563 chapter 28 electrical specifications (mask rom version) .................................... 567 chapter 29 electrical specifications (flash memory version) ........................... 597 chapter 30 electrical specifications (flash memory version (v dd = 2.5 v)) .... 627 chapter 31 characteristics curves (reference values) .................................... 658 chapter 32 package drawings ............................................................................................. 660 chapter 33 recommended soldering conditions ..................................................... 662 appendix a differences between pd78054, 78058f, and 780058 subseries ......... 666 appendix b development tools ........................................................................................... 668 b.1 software package ............................................................................................................. 670 b.2 language processing software ...................................................................................... 670 b.3 control software ............................................................................................................... 671 b.4 flash memory writing tools ............................................................................................ 671 b.5 debugging tools (hardware) ........................................................................................... 672 b.5.1 when using in-circuit emulator ie-78k0-ns, ie-78k0-ns-a .................................................. 672 b.5.2 when using in-circuit emulator ie-78001-r-a ....................................................................... 673 b.6 debugging tools (software) ............................................................................................ 674 b.7 embedded software ......................................................................................................... 675 b.8 system-upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a ................................................................................................................. 676 b.9 drawing and footprint for conversion socket (ev-9200gc-80) ................................ 677 b.10 drawing of conversion adapter (tgk-080sdw, tgc-080sbp) .................................. 679 b.11 cautions on designing target system .......................................................................... 681 appendix c register index ..................................................................................................... 685 c.1 register index (register name) ....................................................................................... 685 c.2 register index (symbol) .................................................................................................... 688 appendix d revision history ................................................................................................. 691 20 user's manual u12013ej3v2ud 3-1 pin i/o circuit list ............................................................................................................................... ..... 64 4-1 pin i/o circuit list ............................................................................................................................... ..... 79 5-1 memory map ( pd780053, 780053(a), 780053y, 780053y(a)) ........................................................... 81 5-2 memory map ( pd780054, 780054(a), 780054y, 780054y(a)) ........................................................... 82 5-3 memory map ( pd780055, 780055(a), 780055y, 780055y(a)) ........................................................... 83 5-4 memory map ( pd780056, 780056(a), 780056y, 780056y(a)) ........................................................... 84 5-5 memory map ( pd780058, 780058b, 780058b(a), 780058by, 780058by(a)) ................................... 85 5-6 memory map ( pd78f0058, 78f0058y) ................................................................................................ 86 5-7 data memory addressing ( pd780053, 780053(a), 780053y, 780053y(a)) ....................................... 90 5-8 data memory addressing ( pd780054, 780054(a), 780054y, 780054y(a)) ....................................... 91 5-9 data memory addressing ( pd780055, 780055(a), 780055y, 780055y(a)) ....................................... 92 5-10 data memory addressing ( pd780056, 780056(a), 780056y, 780056y(a)) ....................................... 93 5-11 data memory addressing ( pd780058, 780058b, 780058b(a), 780058by, 780058by(a)) ............... 94 5-12 data memory addressing ( pd78f0058, 78f0058y) ........................................................................... 95 5-13 program counter format ......................................................................................................................... 96 5-14 program status word format .................................................................................................................. 96 5-15 stack pointer format ............................................................................................................................... 98 5-16 data to be saved to stack memory ........................................................................................................ 98 5-17 data to be reset from stack memory .................................................................................................... 98 5-18 general-purpose register configuration ................................................................................................ 99 6-1 port types ............................................................................................................................... ................ 117 6-2 block diagram of p00 and p07 ............................................................................................................. 123 6-3 block diagram of p01 to p05 ................................................................................................................ 123 6-4 block diagram of p10 to p17 ................................................................................................................ 124 6-5 block diagram of p20, p21, and p23 to p26 ....................................................................................... 125 6-6 block diagram of p22 and p27 ............................................................................................................. 126 6-7 block diagram of p20, p21, and p23 to p26 ....................................................................................... 127 6-8 block diagram of p22 and p27 ............................................................................................................. 128 6-9 block diagram of p30 to p37 ................................................................................................................ 129 6-10 block diagram of p40 to p47 ................................................................................................................ 130 6-11 block diagram of falling edge detector ............................................................................................... 130 6-12 block diagram of p50 to p57 ................................................................................................................ 131 6-13 block diagram of p60 to p63 ................................................................................................................ 133 6-14 block diagram of p64 to p67 ................................................................................................................ 133 6-15 block diagram of p70 ............................................................................................................................ 134 6-16 block diagram of p71 and p72 ............................................................................................................. 135 6-17 block diagram of p120 to p127 ............................................................................................................ 136 6-18 block diagram of p130 and p131 ......................................................................................................... 137 6-19 port mode register format ................................................................................................................... 140 6-20 format of pull-up resistor option register .......................................................................................... 141 6-21 format of memory expansion mode register ...................................................................................... 142 list of figures (1/8) figure no. title page 21 user's manual u12013ej3v2ud 6-22 format of key return mode register ................................................................................................... 143 7-1 clock generator block diagram ............................................................................................................ 147 7-2 subsystem clock feedback resistor ................................................................................................... 148 7-3 format of processor clock control register ........................................................................................ 149 7-4 format of oscillation mode selection register .................................................................................... 151 7-5 main system clock waveform due to writing to osms ...................................................................... 151 7-6 external circuit of main system clock oscillator ................................................................................. 152 7-7 external circuit of subsystem clock oscillator .................................................................................... 153 7-8 examples of resonator with bad connection ...................................................................................... 154 7-9 main system clock stop function ........................................................................................................ 157 7-10 switching between system clock and cpu clock .............................................................................. 161 8-1 block diagram of 16-bit timer/event counter ...................................................................................... 165 8-2 block diagram of 16-bit timer/event counter output controller ........................................................ 166 8-3 format of timer clock select register 0 .............................................................................................. 170 8-4 format of 16-bit timer mode control register .................................................................................... 172 8-5 format of capture/compare control register 0 .................................................................................. 173 8-6 format of 16-bit timer output control register .................................................................................. 175 8-7 format of port mode register 3 ............................................................................................................ 176 8-8 format of external interrupt mode register 0 ...................................................................................... 177 8-9 format of sampling clock select register ........................................................................................... 178 8-10 control register settings for interval timer operation ........................................................................ 179 8-11 interval timer configuration diagram ................................................................................................... 180 8-12 interval timer operation timings .......................................................................................................... 180 8-13 control register settings for pwm output operation ......................................................................... 182 8-14 example of d/a converter configuration with pwm output ............................................................... 183 8-15 tv tuner application circuit example ................................................................................................... 183 8-16 control register settings for ppg output operation ........................................................................... 184 8-17 configuration of ppg output ................................................................................................................. 185 8-18 ppg output operation timing ............................................................................................................... 185 8-19 control register settings for pulse width measurement with free-running counter and one capture register .................................................................................................................... 186 8-20 configuration diagram for pulse width measurement by free-running counter .............................. 187 8-21 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ..................................................................... 187 8-22 control register settings for two pulse width measurements with free-running counter .............. 188 8-23 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................................. 189 8-24 control register settings for pulse width measurement with free-running counter and two capture registers ................................................................................................................... 190 8-25 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) ................................................................... 191 8-26 control register settings for pulse width measurement by means of restart .................................. 192 list of figures (2/8) figure no. title page 22 user's manual u12013ej3v2ud 8-27 timing of pulse width measurement operation by means of restart (with rising edge specified) ................................................................................................................. 192 8-28 control register settings in external event counter mode ................................................................ 193 8-29 external event counter configuration diagram ................................................................................... 194 8-30 external event counter operation timing (with rising edge specified) ............................................ 194 8-31 control register settings in square-wave output mode .................................................................... 195 8-32 square-wave output operation timing ................................................................................................ 196 8-33 control register settings for one-shot pulse output operation using software trigger .................. 197 8-34 one-shot pulse output operation timing using software trigger ..................................................... 198 8-35 control register settings for one-shot pulse output operation using external trigger .................. 199 8-36 one-shot pulse output operation timing using external trigger (with rising edge specified) ...... 200 8-37 16-bit timer register start timing ........................................................................................................ 201 8-38 timing after change of compare register during timer count operation ....................................... 201 8-39 capture register data retention timing .............................................................................................. 202 8-40 operation timing of ovf0 flag ............................................................................................................ 203 9-1 block diagram of 8-bit timer/event counter ........................................................................................ 211 9-2 block diagram of 8-bit timer/event counter output controller 1 ....................................................... 212 9-3 block diagram of 8-bit timer/event counter output controller 2 ....................................................... 212 9-4 format of timer clock select register 1 .............................................................................................. 215 9-5 format of 8-bit timer mode control register 1 ................................................................................... 216 9-6 format of 8-bit timer output control register ..................................................................................... 217 9-7 format of port mode register 3 ............................................................................................................ 218 9-8 interval timer operation timing ............................................................................................................ 219 9-9 external event counter operation timing (with rising edge specified) ............................................ 222 9-10 square-wave output operation timing ................................................................................................ 224 9-11 interval timer operation timing ............................................................................................................ 225 9-12 external event counter operation timing (with rising edge specified) ............................................ 227 9-13 square-wave output operation timing ................................................................................................ 229 9-14 start timing of 8-bit timer registers 1 and 2 ...................................................................................... 230 9-15 external event counter operation timing ............................................................................................ 230 9-16 timing after compare register change during timer count operation ............................................ 231 10-1 watch timer block diagram .................................................................................................................. 234 10-2 format of timer clock select register 2 .............................................................................................. 235 10-3 format of watch timer mode control register .................................................................................... 236 11-1 watchdog timer block diagram ............................................................................................................ 240 11-2 format of timer clock select register 2 .............................................................................................. 242 11-3 format of watchdog timer mode register ........................................................................................... 243 12-1 remote controlled output application example .................................................................................. 246 12-2 clock output controller block diagram ................................................................................................ 247 12-3 format of timer clock select register 0 .............................................................................................. 248 list of figures (3/8) figure no. title page 23 user's manual u12013ej3v2ud 12-4 format of port mode register 3 ............................................................................................................ 249 13-1 buzzer output controller block diagram .............................................................................................. 250 13-2 format of timer clock select register 2 .............................................................................................. 252 13-3 format of port mode register 3 ............................................................................................................ 253 14-1 a/d converter block diagram ............................................................................................................... 255 14-2 format of a/d converter mode register .............................................................................................. 259 14-3 format of a/d converter input select register .................................................................................... 260 14-4 format of external interrupt mode register 1 ...................................................................................... 261 14-5 a/d converter basic operation ............................................................................................................. 263 14-6 relationship between analog input voltage and a/d conversion result ........................................... 264 14-7 a/d conversion by hardware start ....................................................................................................... 265 14-8 a/d conversion by software start ........................................................................................................ 266 14-9 overall error ............................................................................................................................... ............ 267 14-10 quantization error ............................................................................................................................... ... 267 14-11 example of method of reducing current consumption in standby mode ......................................... 269 14-12 analog input pin handling ..................................................................................................................... 270 14-13 a/d conversion end interrupt request generation timing ................................................................. 271 14-14 timing of reading conversion result (when conversion result is undefined) ................................ 272 14-15 timing of reading conversion result (when conversion result is normal) ..................................... 272 14-16 example of connecting capacitor to av ref0 pin .................................................................................. 273 14-17 internal equivalent circuit of pins ani0 to ani7 .................................................................................. 274 14-18 example of connection if signal source impedance is high .............................................................. 274 15-1 d/a converter block diagram ............................................................................................................... 276 15-2 format of d/a converter mode register .............................................................................................. 278 15-3 use example of buffer amplifier ........................................................................................................... 280 16-1 serial bus interface (sbi) system configuration example .................................................................. 283 16-2 block diagram of serial interface channel 0 ....................................................................................... 285 16-3 format of timer clock select register 3 .............................................................................................. 289 16-4 format of serial operating mode register 0 ....................................................................................... 290 16-5 format of serial bus interface control register .................................................................................. 292 16-6 format of interrupt timing specification register ................................................................................ 294 16-7 3-wire serial i/o mode timing .............................................................................................................. 299 16-8 relt and cmdt operations ................................................................................................................. 299 16-9 circuit for switching transfer bit order ................................................................................................. 300 16-10 example of serial bus configuration with sbi ..................................................................................... 301 16-11 sbi transfer timing ............................................................................................................................... . 303 16-12 bus release signal ............................................................................................................................... 304 16-13 command signal ............................................................................................................................... ..... 304 16-14 addresses ............................................................................................................................... ................ 305 16-15 slave selection by address ................................................................................................................... 305 list of figures (4/8) figure no. title page 24 user's manual u12013ej3v2ud 16-16 commands ............................................................................................................................... .............. 306 16-17 data ............................................................................................................................... ......................... 306 16-18 acknowledge signal ............................................................................................................................... 307 16-19 busy and ready signals .................................................................................................................... 308 16-20 relt, cmdt, reld, and cmdd operations (master) ......................................................................... 313 16-21 reld and cmdd operations (slave) ................................................................................................... 313 16-22 ackt operation ............................................................................................................................... ...... 314 16-23 acke operations ............................................................................................................................... .... 315 16-24 ackd operations ............................................................................................................................... .... 316 16-25 bsye operation ............................................................................................................................... ...... 316 16-26 pin configuration ............................................................................................................................... .... 319 16-27 address transmission from master device to slave device (wup = 1) ............................................. 321 16-28 command transmission from master device to slave device ............................................................ 322 16-29 data transmission from master device to slave device ..................................................................... 323 16-30 data transmission from slave device to master device ..................................................................... 324 16-31 serial bus configuration example using 2-wire serial i/o mode ...................................................... 327 16-32 2-wire serial i/o mode timing .............................................................................................................. 330 16-33 relt and cmdt operations ................................................................................................................. 331 16-34 sck0/p27 pin configuration ................................................................................................................. 332 17-1 serial bus configuration example using i 2 c bus ................................................................................ 335 17-2 block diagram of serial interface channel 0 ....................................................................................... 337 17-3 format of timer clock select register 3 .............................................................................................. 341 17-4 format of serial operating mode register 0 ....................................................................................... 342 17-5 format of serial bus interface control register .................................................................................. 343 17-6 format of interrupt timing specification register ................................................................................ 345 17-7 3-wire serial i/o mode timing .............................................................................................................. 350 17-8 relt and cmdt operations ................................................................................................................. 350 17-9 circuit for switching transfer bit order ................................................................................................. 351 17-10 serial bus configuration example using 2-wire serial i/o mode ...................................................... 352 17-11 2-wire serial i/o mode timing .............................................................................................................. 355 17-12 relt and cmdt operations ................................................................................................................. 356 17-13 example of serial bus configuration using i 2 c bus ......................................................................... 357 17-14 i 2 c bus serial data transfer timing ................................................................................................... 358 17-15 start condition ............................................................................................................................... ..... 359 17-16 address ............................................................................................................................... ................ 359 17-17 transfer direction specification .......................................................................................................... 359 17-18 acknowledge signal ............................................................................................................................ 360 17-19 stop condition ............................................................................................................................... ...... 360 17-20 wait signal ............................................................................................................................... ........... 361 17-21 pin configuration ............................................................................................................................... . 366 17-22 data transmission from master to slave (both master and slave selected 9-clock wait) ............ 368 17-23 data transmission from slave to master (both master and slave selected 9-clock wait) ............ 371 17-24 start condition output ........................................................................................................................ 374 list of figures (5/8) figure no. title page 25 user's manual u12013ej3v2ud 17-25 slave wait release (transmission) .................................................................................................... 375 17-26 slave wait release (reception) ......................................................................................................... 376 17-27 sck0/scl/p27 pin configuration ...................................................................................................... 380 17-28 sck0/scl/p27 pin configuration ...................................................................................................... 380 17-29 logic circuit of scl signal ................................................................................................................ 381 18-1 block diagram of serial interface channel 1 ....................................................................................... 384 18-2 format of timer clock select register 3 .............................................................................................. 387 18-3 format of serial operation mode register 1 ....................................................................................... 388 18-4 format of automatic data transmit/receive control register ............................................................ 389 18-5 format of automatic data transmit/receive interval specification register ...................................... 390 18-6 3-wire serial i/o mode timing .............................................................................................................. 396 18-7 circuit for switching transfer bit order ................................................................................................. 397 18-8 basic transmission/reception mode operation timing ....................................................................... 406 18-9 basic transmission/reception mode flowchart ................................................................................... 407 18-10 internal buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) ......................................................................................................... 408 18-11 basic transmission mode operation timing ......................................................................................... 410 18-12 basic transmission mode flowchart ..................................................................................................... 411 18-13 internal buffer ram operation in 6-byte transmission (in basic transmit mode) ............................. 412 18-14 repeat transmission mode operation timing ...................................................................................... 414 18-15 repeat transmission mode flowchart .................................................................................................. 415 18-16 internal buffer ram operation in 6-byte transmission (in repeat transmit mode) ........................... 416 18-17 automatic transmission/reception suspension and restart .............................................................. 418 18-18 system configuration when busy control option is used .................................................................. 419 18-19 operation timing when busy control option is used (when busy0 = 0) ........................................ 420 18-20 busy signal and wait release (when busy0 = 0) ............................................................................. 421 18-21 operation timing when busy & strobe control options are used (when busy0 = 0) .................... 422 18-22 operation timing of bit shift detection function by busy signal (when busy0 = 1) ...................... 423 18-23 automatic data transmit/receive interval time ................................................................................... 424 18-24 operation timing with automatic data transmit/receive function performed using internal clock ............................................................................................................................... .......... 425 19-1 block diagram of serial interface channel 2 ....................................................................................... 429 19-2 baud rate generator block diagram ................................................................................................... 430 19-3 format of serial operating mode register 2 ....................................................................................... 432 19-4 format of asynchronous serial interface mode register .................................................................... 433 19-5 format of asynchronous serial interface status register ................................................................... 436 19-6 format of baud rate generator control register ................................................................................ 437 19-7 format of serial interface pin select register ..................................................................................... 441 19-8 format of asynchronous serial interface transmit/receive data ....................................................... 452 19-9 asynchronous serial interface transmission completion interrupt request generation timing ....... 454 19-10 asynchronous serial interface reception completion interrupt request generation timing ........... 455 19-11 receive error timing ............................................................................................................................. 45 6 list of figures (6/8) figure no. title page 26 user's manual u12013ej3v2ud 19-12 status of receive buffer register (rxb) and generation of interrupt request (intsr) when reception is stopped .................................................................................................................. 457 19-13 3-wire serial i/o mode timing .............................................................................................................. 463 19-14 circuit for switching transfer bit order ................................................................................................. 464 19-15 reception completion interrupt request generation timing (when isrm = 1) ................................ 465 19-16 receive buffer register read disable period ...................................................................................... 466 19-17 p23 output selector .............................................................................................................................. 4 68 20-1 real-time output port block diagram .................................................................................................. 470 20-2 real-time output buffer register configuration .................................................................................. 471 20-3 format of port mode register 12 .......................................................................................................... 472 20-4 format of real-time output port mode register ................................................................................ 472 20-5 format of real-time output port control register .............................................................................. 473 21-1 basic configuration of interrupt function ............................................................................................. 477 21-2 format of interrupt request flag register ........................................................................................... 480 21-3 interrupt mask flag register format .................................................................................................... 481 21-4 format of priority specification flag register ...................................................................................... 482 21-5 format of external interrupt mode register 0 ...................................................................................... 483 21-6 format of external interrupt mode register 1 ...................................................................................... 484 21-7 format of sampling clock select register ........................................................................................... 485 21-8 noise eliminator i/o timing (during rising edge detection) .............................................................. 486 21-9 format of program status word ........................................................................................................... 487 21-10 non-maskable interrupt request occurrence and acknowledgment flowchart ................................ 489 21-11 non-maskable interrupt request acknowledgment timing ................................................................. 489 21-12 non-maskable interrupt request acknowledgment operation ............................................................ 490 21-13 interrupt request acknowledgment processing algorithm .................................................................. 492 21-14 interrupt request acknowledgment timing (minimum time) .............................................................. 493 21-15 interrupt request acknowledgment timing (maximum time) ............................................................. 493 21-16 multiple interrupt servicing example .................................................................................................... 495 21-17 interrupt request pending timing ......................................................................................................... 497 21-18 basic configuration of test function .................................................................................................... 498 21-19 format of interrupt request flag register 1l ...................................................................................... 499 21-20 format of interrupt mask flag register 1l .......................................................................................... 499 21-21 format of key return mode register ................................................................................................... 500 22-1 memory map when using external device expansion function ........................................................ 502 22-2 format of memory expansion mode register ...................................................................................... 505 22-3 format of internal memory size switching register ............................................................................ 506 22-4 instruction fetch from external memory ............................................................................................... 508 22-5 external memory read timing .............................................................................................................. 509 22-6 external memory write timing .............................................................................................................. 510 22-7 external memory read modify write timing ........................................................................................ 511 22-8 example of connection between pd780054 and memory ................................................................ 512 list of figures (7/8) figure no. title page 27 user's manual u12013ej3v2ud 23-1 format of oscillation stabilizat time selection register ..................................................................... 514 23-2 halt mode release by interrupt request generation ........................................................................ 516 23-3 halt mode release by reset input .................................................................................................. 517 23-4 stop mode release by interrupt request generation ....................................................................... 519 23-5 stop mode release by reset input ................................................................................................. 520 24-1 reset function block diagram .............................................................................................................. 521 24-2 reset timing by reset input .............................................................................................................. 522 24-3 reset timing due to watchdog timer overflow ................................................................................... 522 24-4 reset timing by reset input in stop mode ..................................................................................... 522 25-1 rom correction block diagram ............................................................................................................ 525 25-2 format of correction address registers 0 and 1 ................................................................................. 526 25-3 format of correction control register .................................................................................................. 527 25-4 example of storing to eeprom (when one place is corrected) ...................................................... 528 25-5 initialization routine ............................................................................................................................... 529 25-6 rom correction operation .................................................................................................................... 530 25-7 rom correction usage example .......................................................................................................... 531 25-8 program transition diagram (when one place is corrected) ............................................................. 532 25-9 program transition diagram (when two places are corrected) ......................................................... 533 26-1 format of memory size switching register ......................................................................................... 536 26-2 format of internal expansion ram size switching register .............................................................. 537 23-3 environment for writing program to flash memory ............................................................................. 538 26-4 communication mode selection format ............................................................................................... 539 26-5 example of connection with dedicated flash programmer ................................................................ 540 26-6 v pp pin connection example ................................................................................................................ 543 26-7 signal conflict (input pin of serial interface) ....................................................................................... 544 26-8 abnormal operation of other device .................................................................................................... 544 26-9 signal conflict (reset pin) .................................................................................................................. 545 26-10 wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-0) .............................. 546 26-11 wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-1) .............................. 547 26-12 wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-2) .............................. 548 26-13 wiring example for flash writing adapter in uart mode (uart ch-0) ............................................. 549 26-14 wiring example for flash writing adapter in uart mode (uart ch-1) ............................................. 550 26-15 wiring example for flash writing adapter in pseudo 3-wire mode .................................................... 551 b-1 configuration of development tools ..................................................................................................... 669 b-2 ev-9200gc-80 drawing (for reference only) ..................................................................................... 677 b-3 ev-9200gc-80 footprint (for reference only) ................................................................................... 678 b-4 tgk-080sdw drawing (for reference only) (unit: mm) .................................................................... 679 b-5 tgc-080sbp drawing (for reference only) (unit: mm) ................................................................... 680 b-6 distance between in-circuit emulator and conversion socket (80gc) .............................................. 681 b-7 connection condition of target system (np-80gc-tq) ...................................................................... 682 b-8 distance between in-circuit emulator and conversion socket (80gk) .............................................. 683 b-9 connection condition of target system (np-80gk) ............................................................................ 684 list of figures (8/8) figure no. title page 28 user's manual u12013ej3v2ud 1-1 mask options of mask rom versions .................................................................................................... 40 1-2 differences between standard model and (a) model ............................................................................ 40 2-1 mask options of mask rom versions .................................................................................................... 50 2-2 differences between standard model and (a) model ............................................................................ 50 3-1 pin i/o circuit types ............................................................................................................................... .62 4-1 pin i/o circuit types ............................................................................................................................... .77 5-1 vector ............................................................................................................................... ......................... 88 5-2 special-function register list .............................................................................................................. 101 6-1 port functions ( pd780058 subseries) ............................................................................................... 118 6-2 port functions ( pd780058y subseries) ............................................................................................. 120 6-3 port configuration ............................................................................................................................... ... 122 6-4 pull-up resistor of port 6 ...................................................................................................................... 132 6-5 port mode register and output latch settings when using alternate functions ............................. 139 6-6 comparison between mask rom version and flash memory version .............................................. 145 7-1 clock generator configuration .............................................................................................................. 146 7-2 relationship between cpu clock and minimum instruction execution time ..................................... 150 7-3 maximum time required for cpu clock switchover ........................................................................... 160 8-1 16-bit timer/event counter interval times ........................................................................................... 162 8-2 16-bit timer/event counter square-wave output ranges .................................................................. 163 8-3 16-bit timer/event counter configuration ............................................................................................ 164 8-4 intp0/ti00 pin valid edge and cr00 capture trigger valid edge ..................................................... 167 8-5 intp1/ti01 pin valid edge and cr00 capture trigger valid edge ..................................................... 167 8-6 intp0/ti00 pin valid edge and cr01 capture trigger valid edge ..................................................... 168 8-7 16-bit timer/event counter interval times ........................................................................................... 181 8-8 16-bit timer/event counter square-wave output ranges .................................................................. 196 9-1 interval times of 8-bit timer/event counters 1 and 2 ......................................................................... 206 9-2 square-wave output ranges of 8-bit timer/event counters 1 and 2 ................................................ 207 9-3 interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counter ................................................................................................................... 208 9-4 square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counter ............................................................................................. 209 9-5 8-bit timer/event counter configuration .............................................................................................. 210 9-6 interval time of 8-bit timer/event counter 1 ....................................................................................... 220 9-7 interval time of 8-bit timer/event counter 2 ....................................................................................... 221 9-8 square-wave output ranges of 8-bit timer/event counters 1 and 2 ................................................ 223 list of tables (1/3) table no. title page 29 user's manual u12013ej3v2ud 9-9 interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter ............................................................................................. 226 9-10 square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter ............................................................................................. 228 10-1 interval timer interval time ................................................................................................................... 232 10-2 watch timer configuration .................................................................................................................... 233 10-3 interval timer interval time ................................................................................................................... 237 11-1 watchdog timer program loop detection times ................................................................................. 238 11-2 interval times ............................................................................................................................... .......... 239 11-3 watchdog timer configuration .............................................................................................................. 240 11-4 watchdog timer program loop detection time ................................................................................... 244 11-5 interval timer interval time ................................................................................................................... 245 12-1 clock output controller configuration .................................................................................................. 247 13-1 buzzer output controller configuration ................................................................................................ 250 14-1 a/d converter configuration ................................................................................................................. 254 14-2 a/d converter sampling time and a/d conversion start delay time ................................................ 263 14-3 resistances and capacitances of equivalent circuit (reference values) .......................................... 274 15-1 d/a converter configuration ................................................................................................................. 276 16-1 differences between channels 0, 1, and 2 .......................................................................................... 281 16-2 configuration of serial interface channel 0 ......................................................................................... 284 16-3 various signals in sbi mode ................................................................................................................. 317 17-1 differences between channels 0, 1, and 2 .......................................................................................... 333 17-2 configuration of serial interface channel 0 ......................................................................................... 336 17-3 interrupt request signal generation of serial interface channel 0 .................................................... 339 17-4 signals in i 2 c bus mode ..................................................................................................................... 365 18-1 configuration of serial interface channel 1 ......................................................................................... 383 18-2 interval timing according to cpu processing (when internal clock is operating) ........................... 425 18-3 interval time according to cpu processing (with external clock) ..................................................... 426 19-1 configuration of serial interface channel 2 ......................................................................................... 428 19-2 operating mode settings of serial interface channel 2 ...................................................................... 434 19-3 relationship between main system clock and baud rate ................................................................. 439 19-4 relationship between asck pin input frequency and baud rate (when brgc is set to 00h) ..... 440 19-5 relationship between main system clock and baud rate ................................................................. 449 19-6 relationship between asck pin input frequency and baud rate (when brgc is set to 00h) ..... 450 list of tables (2/3) table no. title page 30 user's manual u12013ej3v2ud 19-7 receive error causes ............................................................................................................................ 456 20-1 real-time output port configuration .................................................................................................... 470 20-2 operation in real-time output buffer register manipulation ............................................................. 471 20-3 real-time output port operating mode and output trigger ............................................................... 473 21-1 interrupt source list .............................................................................................................................. 4 75 21-2 various flags corresponding to interrupt request sources ............................................................... 479 21-3 times from maskable interrupt request generation to interrupt servicing ....................................... 491 21-4 interrupt request enabled for multiple interrupt servicing during interrupt servicing ...................... 494 21-5 test input sources ............................................................................................................................... .. 498 21-6 flags corresponding to test input signals ........................................................................................... 498 22-1 pin functions in external memory expansion mode ........................................................................... 501 22-2 state of port 4 to 6 pins in external memory expansion mode .......................................................... 501 22-3 values after internal memory size switching register is reset ......................................................... 506 23-1 halt mode operating status ................................................................................................................ 515 23-2 operation after halt mode release .................................................................................................... 517 23-3 stop mode operating status ............................................................................................................... 518 23-4 operation after stop mode release ................................................................................................... 520 24-1 hardware status after reset ................................................................................................................. 523 25-1 rom correction configuration .............................................................................................................. 525 26-1 differences between pd78f0058, 78f0058y and mask rom versions .......................................... 535 26-2 internal memory size switching register setting values .................................................................... 536 26-3 internal expansion ram size switching register setting values ....................................................... 537 26-4 communication mode list ..................................................................................................................... 539 26-5 pin connection list ............................................................................................................................... . 542 27-1 operand identifiers and description methods ...................................................................................... 553 33-1 surface mounting type soldering conditions ....................................................................................... 662 a-1 major differences between pd78054, 78058f, and 780058 subseries ........................................... 666 b-1 system-upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a ......... 676 list of tables (3/3) table no. title page 31 user's manual u12013ej3v2ud chapter 1 outline ( pd780058 subseries) 1.1 features on-chip high-capacity rom and ram item program memory data memory mask rom flash internal high- internal buffer internal part number memory speed ram ram expansion ram pd780053, 780053(a) 24 kb 1,024 bytes 32 bytes none pd780054, 780054(a) 32 kb pd780055, 780055(a) 40 kb pd780056, 780056(a) 48 kb pd780058, 780058b, 780058b(a) 60 kb 1,024 bytes pd78f0058 60 kb note 1 1,024 bytes note 2 notes 1. the flash memory capacity can be changed by means of the internal memory size switching register (ims). 2. the capacity of the internal high-speed ram can be changed by means of the internal expansion ram size switching register (ixs). external memory expansion space: 64 kb minimum instruction execution time changeable from high-speed (0.4 s: main system clock 5.0 mhz operation) to ultra-low speed (122 s: subsystem clock 32.768 khz operation) instruction set suited to system control ?bit manipulation possible in all address spaces ?multiple and divide instructions i/o ports: 68 (n-ch open-drain: 4) 8-bit resolution a/d converter: 8 channels (v dd = 1.8 to 5.5 v note ) 8-bit resolution d/a converter: 2 channels (v dd = 1.8 to 5.5 v note ) serial interface: 3 channels ?3-wire serial i/o/sbi/2-wire serial i/o mode: 1 channel ?3-wire serial i/o mode (on-chip automatic transmit/receive function): 1 channel ?3-wire serial i/o/uart mode (on-chip time-division transfer function): 1 channel timer: 5 channels ?16-bit timer/event counter: 1 channel ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel note the operating voltage range of the a/d and d/a converters of the pd780058 is v dd = 2.7 to 5.5 v. 32 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud vectored interrupt sources: 21 test inputs: 2 two types of on-chip clock oscillators (main system clock and subsystem clock) supply voltage: v dd = 1.8 to 5.5 v (mask rom version) v dd = 2.7 note to 5.5 v ( pd78f0058) note v dd = 2.2 v can also be supplied to the pd78f0058. for details, contact an nec electronics sales representative. 1.2 applications car audio systems, cellular phones, pagers, printers, av equipment, cameras, ppcs, vending machines, car electrical components, etc. 1.3 ordering information part number package internal rom pd780053gc- -8bt 80-pin plastic qfp (14 14) mask rom pd780053gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780054gc- -8bt 80-pin plastic qfp (14 14) mask rom pd780054gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780055gc- -8bt 80-pin plastic qfp (14 14) mask rom pd780055gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780056gc- -8bt 80-pin plastic qfp (14 14) mask rom pd780056gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780058gc- -8bt 80-pin plastic qfp (14 14) mask rom pd780058gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780058bgc- -8bt 80-pin plastic qfp (14 14) mask rom pd780058bgk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780053gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780054gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780055gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780056gc(a)- -8bt 80-pin plastic qfp (14 14) special pd780058bgc(a)- -8bt 80-pin plastic qfp (14 14) special pd78f0058gc-8bt 80-pin plastic qfp (14 14) flash memory pd78f0058gk-9eu 80-pin plastic tqfp (fine pitch) (12 12) flash memory remark indicates rom code suffix. for details of the quality grades and their applications, see quality grades on nec electronics semiconductor devices (document no.: c11531e). 33 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud 1.4 pin configuration (top view) 80-pin plastic qfp (14 14) pd780053gc- -8bt, 780054gc- -8bt, 780055gc- -8bt, pd780056gc- -8bt, 780058gc- -8bt, 780058bgc- -8bt, pd780053gc(a)- -8bt, 780054gc(a)- -8bt, 780055gc(a)- -8bt, pd780056gc(a)- -8bt, 780058bgc(a)- -8bt, 78f0058gc-8bt 80-pin plastic tqfp (fine pitch) (12 12) pd780053gk- -9eu, 780054gk- -9eu, 780055gk- -9eu, pd780056gk- -9eu, 780058gk- -9eu, 780058bgk- -9eu, 78f0058gk-9eu cautions 1. be sure to connect the ic (internally connected) pin to v ss0 or v ss1 directly in the normal operating mode. 2. connect the av ss pin to v ss0 . remarks 1. the pin connection in parentheses is intended for the pd78f0058. 2. when the pd780053, 780054, 780055, 780056, 780058, or 780058b is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0 p26/so0/sb1 p27/sck0 p40/ad0 p41/ad1 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 v dd0 xt1/p07 xt2 ic (v pp ) x1 x2 v dd1 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss1 p56/a14 p57/a15 p60 p61 p62 p63 p64/rd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v ss0 34 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud a8 to a15: address bus pcl: programmable clock ad0 to ad7: address/data bus rd: read strobe ani0 to ani7: analog input reset: reset ano0, ano1: analog output rtp0 to rtp7: real-time output port asck: asynchronous serial clock rxd0, rxd1: receive data astb: address strobe sb0, sb1: serial bus av ref0 , av ref1 : analog reference voltage sck0 to sck2: serial clock av ss : analog ground si0 to si2: serial input busy: busy so0 to so2: serial output buz: buzzer clock stb: strobe ic: internally connected ti00, ti01: timer input intp0 to intp6: interrupt from peripherals ti1, ti2: timer input p00 to p05, p07: port 0 to0 to to2: timer output p10 to p17: port 1 txd0, txd1: transmit data p20 to p27: port 2 v dd0 , v dd1 : power supply p30 to p37: port 3 v pp : programming power supply p40 to p47: port 4 v ss0 , v ss1 : ground p50 to p57: port 5 wait: wait p60 to p67: port 6 wr: write strobe p70 to p72: port 7 x1, x2: crystal (main system clock) p120 to p127: port 12 xt1, xt2: crystal (subsystem clock) p130, p131: port 13 35 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud 1.5 78k/0 series lineup 78k/0 series product lineup is illustrated below. part numbers in the boxes indicate subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703y pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y 36 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud the following lists the main functional differences between subseries products. non-y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd780034as 4 ch 39 pd780024as 4 ch pd78014h 8 ch 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780354 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 66 1.8 v drive pd780344 8 ch pd780338 48 k to 60 k 3 ch 2 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v supported pd780816 32 k to 60 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash- pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value capacity (bytes) 37 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud 1.6 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. the pin connection in parentheses is intended for the pd78f0058. 16-bit timer/ event counter 8-bit timer/ event counter 1 watchdog timer watch timer serial interface 0 serial interface 1 a/d converter d/a converter 8-bit timer/ event counter 2 interrupt control buzzer output clock output control v dd0 , v ss0 , ic (v pp ) 78k/0 cpu core rom (flash memory) ram port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 real-time output port external access system control p00 p01 to p05 p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p72 p120 to p127 p130, p131 rtp0/p120 to rtp7/p127 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2 to0/p30 ti00/p00 ti01/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/txd1/p23 busy/rxd1/p24 si2/rxd0/p70 so2/txd0/p71 sck2/asck/p72 av ss av ref0 ani0/p10 to ani7/p17 ano0/p130, ano1/p131 av ss av ref1 intp0/p00 to intp5/p05 buz/p36 pcl/p35 v dd1 v ss1 busy/rxd1/p24 stb/txd1/p23 serial interface 2 38 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud 1.7 outline of function rom mask rom flash memory 24 kb 32 kb 40 kb 48 kb 60 kb 60 kb note 1 high-speed ram 1,024 bytes buffer ram 32 bytes expansion ram none 1,024 bytes 1,024 bytes note 2 memory space 64 kb general-purpose registers 8 bits 8 4 banks minimum instruction execution time function to vary minimum instruction execution time incorporated with main system clock selected 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 mhz operation) with subsystem clock selected 122 s (@ 32.768 khz operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 68 cmos input: 2 cmos i/o: 62 n-ch open-drain i/o: 4 a/d converter 8-bit resolution 8 channels operating voltage range v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v d/a converter 8-bit resolution 2 channels operating voltage range v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v serial interface 3-wire serial i/o/sbi/2-wire serial i/o mode selection possible: 1 channel 3-wire serial i/o mode (on-chip max. 32 bytes auto-transmit/receive function): 1 channel 3-wire serial i/o/uart mode (on-chip time-division transfer function) selectable: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3: (14-bit pwm output enable: 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (main system clock: @ 5.0 mhz operation) 32.768 khz (subsystem clock: @ 32.768 khz operation) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (main system clock: @ 5.0 mhz operation) notes 1. the capacity of the flash memory can be changed by using the internal memory switching register (ims). 2. the capacity of the internal expansion ram can be changed by using the internal expansion ram size switching register (ixs). item part number internal memory pd780053, pd780054, pd780055, pd780056, pd780058b, pd780058 pd78f0058 780053(a) 780054(a) 780055(a) 780056(a) 780058b(a) 39 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud maskable internal: 13, external: 6 non-maskable internal: 1 software 1 test input internal: 1, external: 1 supply voltage v dd = 1.8 to 5.5 v v dd = 2.7 note to 5.5 v operating ambient temperature t a = 40 to +85 c package 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) note v dd = 2.2 v can also be supplied. for details, contact an nec electronics sales representative. the timers are outlined below. item part number pd780053, pd780054, pd780055, pd780056, pd780058b, pd780058 pd78f0058 780053(a) 780054(a) 780055(a) 780056(a) 780058b(a) vectored interrupt sources operating interval timer 2 channels note 3 2 channels 1 channel note 1 1 channel note 2 mode external event counter ? function timer output ? pwm output pulse width measurement square-wave output ? one-shot pulse output interrupt request ??? test input notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function. 3. when capture/compare registers 00 and 01 (cr00 and cr01) are specified as compare registers. 16-bit timer/ 8-bit timer/event watch timer watchdog timer event counter counters 1 and 2 40 chapter 1 outline ( pd780058 subseries) user's manual u12013ej3v2ud 1.8 mask options the mask rom versions ( pd780053, 780053(a), 780054, 780054(a), 780055, 780055(a), 780056, 780056(a), 780058, 780058b, 780058b(a)) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780058 subseries are shown in table 1-1. table 1-1. mask options of mask rom versions pin names mask options p60 to p63 pull-up resistor connection can be specified in 1-bit units. 1.9 differences between standard model and (a) model the (a) models of the pd780058 subseries ( pd780053(a), 780054(a), 780055(a), 780056(a), and 780058b(a)) have improved reliability by increasing the check items from the standard model ( pd780053, 780054, 780055, 780056, and 780058b). the functions and electrical characteristics of the (a) model are the same as those of the standard model. table 1-2. differences between standard model and (a) model product name standard model (a) model item quality grade standard special (for general-purpose electronic systems) (for high-reliability electronic systems) 41 user's manual u12013ej3v2ud chapter 2 outline ( pd780058y subseries) 2.1 features on-chip high-capacity rom and ram item program memory data memory mask rom flash internal high- internal buffer internal part number memory speed ram ram expansion ram pd780053y, 780053y(a) 24 kb 1,024 bytes 32 bytes none pd780054y, 780054y(a) 32 kb pd780055y, 780055y(a) 40 kb pd780056y, 780056y(a) 48 kb pd780058by, 780058by(a) 60 kb 1,024 bytes pd78f0058y 60 kb note 1 1,024 bytes note 2 notes 1. the capacity of flash memory can be changed by means of the internal memory size switching register (ims). 2. the capacity of internal high-speed ram can be changed by means of the internal expansion ram size switching register (ixs). external memory expansion space: 64 kb minimum instruction execution time changeable from high-speed (0.4 s: main system clock 5.0 mhz operation) to ultra-low speed (122 s: subsystem clock 32.768 khz operation) instruction set suited to system control ?bit manipulation possible in all address spaces ?multiple and divide instructions i/o ports: 68 (n-ch open-drain: 4) 8-bit resolution a/d converter: 8 channels (v dd = 1.8 to 5.5 v) 8-bit resolution d/a converter: 2 channels (v dd = 1.8 to 5.5 v) serial interface: 3 channels ?3-wire serial i/o/2-wire serial i/o/i 2 c bus mode: 1 channel ?3-wire serial i/o mode (on-chip automatic transmit/receive function): 1 channel ?3-wire serial i/o/uart mode (on-chip time-division transfer function): 1 channel timer: 5 channels ?16-bit timer/event counter: 1 channel ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel vectored interrupt sources: 21 test inputs: 2 two types of on-chip clock oscillators (main system clock and subsystem clock) supply voltage: v dd = 1.8 to 5.5 v (mask rom version) v dd = 2.7 note to 5.5 v ( pd78f0058y) note v dd = 2.2 v can also be supplied to the pd78f0058y. for details, contact an nec electronics sales representative. 42 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.2 applications car audio systems, cellular phones, pagers, printers, av equipment, cameras, ppcs, vending machines, car electrical components, etc. 2.3 ordering information part number package internal rom pd780053ygc- -8bt 80-pin plastic qfp (14 14) mask rom pd780053ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780054ygc- -8bt 80-pin plastic qfp (14 14) mask rom pd780054ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780055ygc- -8bt 80-pin plastic qfp (14 14) mask rom pd780055ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780056ygc- -8bt 80-pin plastic qfp (14 14) mask rom pd780056ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780058bygc- -8bt 80-pin plastic qfp (14 14) mask rom pd780058bygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) mask rom pd780053ygc(a)- -8bt 80-pin plastic qfp (14 14) special pd780054ygc(a)- -8bt 80-pin plastic qfp (14 14) special pd780055ygc(a)- -8bt 80-pin plastic qfp (14 14) special pd780056ygc(a)- -8bt 80-pin plastic qfp (14 14) special pd780058bygc(a)- -8bt 80-pin plastic qfp (14 14) special pd78f0058ygc-8bt note 80-pin plastic qfp (14 14) flash-memory pd78f0058ygk-9eu note 80-pin plastic tqfp (fine pitch) (12 12) flash-memory remark indicates rom code suffix. for details of the quality grades and their applications, see quality grades on nec electronics semiconductor devices (document no.: c11531e). 43 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.4 pin configuration (top view) 80-pin plastic qfp (14 14) pd780053ygc- -8bt, 780054ygc- -8bt, 780055ygc- -8bt, pd780056ygc- -8bt, 780058bygc- -8bt, 780053ygc(a)- -8bt, pd780054ygc(a)- -8bt, 780055ygc(a)- -8bt, 780056ygc(a)- -8bt, pd780058bygc(a)- -8bt, 78f0058ygc-8bt 80-pin plastic tqfp (fine pitch) (12 12) pd780053ygk- -9eu, 780054ygk- -9eu, 780055ygk- -9eu, pd780056ygk- -9eu, 780058bygk- -9eu, 78f0058ygk-9eu cautions 1. be sure to connect the ic (internally connected) pin to v ss0 directly in the normal operating mode. 2. connect the av ss pin to v ss0 . remarks 1. the pin connection in parentheses is intended for the pd78f0058y. 2. when the pd780053y, 780054y, 780055y, 780056y, or 780058by is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p40/ad0 p41/ad1 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 v dd0 xt1/p07 xt2 ic (v pp ) x1 x2 v dd1 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss1 p56/a14 p57/a15 p60 p61 p62 p63 p64/rd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v ss0 44 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud a8 to a15: address bus rd: read strobe ad0 to ad7: address/data bus reset: reset ani0 to ani7: analog input rtp0 to rtp7: real-time output port ano0, ano1: analog output rxd0, rxd1: receive data asck: asynchronous serial clock sb0, sb1: serial bus astb: address strobe sck0 to sck2: serial clock av ref0 , av ref1 : analog reference voltage scl: serial clock av ss : analog ground sda0, sda1: serial data busy: busy si0 to si2: serial input buz: buzzer clock so0 to so2: serial output ic: internally connected stb: strobe intp0 to intp6: interrupt from peripherals ti00, ti01: timer input p00 to p05, p07: port 0 ti1, ti2: timer input p10 to p17: port 1 to0 to to2: timer output p20 to p27: port 2 txd0, txd1: transmit data p30 to p37: port 3 v dd0 , v dd1 : power supply p40 to p47: port 4 v pp : programming power supply p50 to p57: port 5 v ss0 , v ss1 : ground p60 to p67: port 6 wait: wait p70 to p72: port 7 wr: write strobe p120 to p127: port 12 x1, x2: crystal (main system clock) p130, p131: port 13 xt1, xt2: crystal (subsystem clock) pcl: programmable clock 45 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.5 78k/0 series lineup 78k/0 series product lineup is illustrated below. part numbers in the boxes indicate subseries names. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703y pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y 46 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud major functional differences among the y subseries are shown below. ? y subseries function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 88 1.8 v pd78070ay 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c: 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch ) 68 1.8 v pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, i 2 c: 1 ch) 69 2.7 v pd78054y 16 k to 60 k 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, i 2 c: 1 ch) 52 1.8 v pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 51 pd780024ay 8 ch pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780354y 24 k to 32 k 4 ch 1 ch 1 ch 1 ch 8 ch 4 ch (uart: 1 ch, 66 1.8 v drive pd780344y 8 ch i 2 c: 1 ch) pd780308y 48 k to 60 k 2 ch 3 ch (time-division uart: 1 ch, i 2 c: 1 ch) 57 2.0 v pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, i 2 c: 1 ch) 67 3.5 v interface pd780703y supported pd780833y 65 4.5 v remark functions other than the serial interface are common to both the y and non-y subseries. v dd min. value rom capacity (bytes) 47 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.6 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. the pin connection in parentheses is intended for the pd78f0058y. 16-bit timer/ event counter 8-bit timer/ event counter 1 watchdog timer watch timer serial interface 0 serial interface 1 a/d converter d/a converter 8-bit timer/ event counter 2 interrupt control buzzer output clock output control v dd0 , v ss0 , ic (v pp ) 78k/0 cpu core rom (flash memory) ram port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 real-time output port external access system control p00 p01 to p05 p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p72 p120 to p127 p130, p131 rtp0/p120 to rtp7/p127 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2 to0/p30 ti00/p00 ti01/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/txd1/p23 busy/rxd1/p24 si2/rxd0/p70 so2/txd0/p71 sck2/asck/p72 av ss av ref0 ani0/p10 to ani7/p17 ano0/p130, ano1/p131 av ss av ref1 intp0/p00 to intp5/p05 buz/p36 pcl/p35 v dd1 v ss1 busy/rxd1/p24 stb/txd1/p23 serial interface 2 48 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.7 outline of functions rom mask rom flash memory 24 kb 32 kb 40 kb 48 kb 60 kb 60 kb note 1 high-speed ram 1,024 bytes buffer ram 32 bytes expansion ram none 1,024 bytes 1,024 bytes note 2 memory space 64 kb general-purpose registers 8 bits 8 4 banks minimum instruction execution time function to vary minimum instruction execution time incorporated with main system clock selected 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 mhz operation) with subsystem clock selected 122 s (@ 32.768 khz operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, and boolean operation) bcd adjust, etc. i/o ports total: 68 cmos input: 2 cmos i/o: 62 n-ch open-drain i/o: 4 a/d converter 8-bit resolution 8 channels operating voltage range v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v d/a converter 8-bit resolution 2 channels operating voltage range v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v serial interface 3-wire serial i/o/sbi/2-wire serial i/o mode selection possible: 1 channel 3-wire serial i/o mode (on-chip max. 32 bytes auto-transmit/receive function): 1 channel 3-wire serial i/o/uart mode (on-chip time-division transfer function) selectable: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3: (14-bit pwm output enable: 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (main system clock: @ 5.0 mhz operation) 32.768 khz (subsystem clock: @ 32.768 khz operation) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (main system clock: @ 5.0 mhz operation) notes 1. the capacity of the flash memory can be changed by using the internal memory switching register (ims). 2. the capacity of the internal expansion ram can be changed by using the internal expansion ram size switching register (ixs). item part number internal memory pd780053y, pd780054y, pd780055y, pd780056y, pd780058by pd78f0058y 780053y(a) 780054y(a) 780055y(a) 780056y(a) 780058by(a) 49 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud maskable internal: 13, external: 6 non-maskable internal: 1 software 1 test input internal: 1, external: 1 supply voltage v dd = 1.8 to 5.5 v v dd = 2.7 note to 5.5 v operating ambient temperature t a = 40 to +85 c package 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) note v dd = 2.2 v can also be supplied. for details, contact an nec electronics sales representative. the timers are outlined below. item part number pd780053y, pd780054y, pd780055y, pd780056y, pd780058by pd78f0058y 780053y(a) 780054y(a) 780055y(a) 780056y(a) 780058by(a) vectored interrupt sources operating interval timer 2 channels note 3 2 channels 1 channel note 1 1 channel note 2 mode external event counter ? function timer output ? pwm output pulse width measurement square-wave output ? one-shot pulse output interrupt request ??? test input notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function. 3. when capture/compare registers 00 and 01 (cr00 and cr01) are specified as compare registers. 16-bit timer/ 8-bit timer/event watch timer watchdog timer event counter counters 1 and 2 50 chapter 2 outline ( pd780058y subseries) user's manual u12013ej3v2ud 2.8 mask options the mask rom versions ( pd780053y, 780053y(a), 780054y, 780054y(a), 780055y, 780055y(a), 780056y, 780056y(a), 780058by, 780058by(a)) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780058y subseries are shown in table 2-1. table 2-1. mask options of mask rom versions pin names mask options p60 to p63 pull-up resistor connection can be specified in 1-bit units. 2.9 differences between standard model and (a) model the (a) models of the pd780058y subseries ( pd780053y(a), 780054y(a), 780055y(a), 780056y(a), and 780058by(a)) have improved reliability by increasing the check items from the standard model ( pd780053y, 780054y, 780055y, 780056y, and 780058by). the functions and electrical characteristics of the (a) model are the same as those of the standard model. table 2-2. differences between standard model and (a) model product name standard model (a) model item quality grade standard special (for general-purpose electronic systems) (for high-reliability electronic systems) 51 user's manual u12013ej3v2ud pin name i/o function after reset alternate function p00 input port 0 input only input intp0/ti00 p01 input intp1/ti01 p02 intp2 p03 intp3 p04 intp4 p05 intp5 p07 note 1 input input only input xt1 p10 to p17 i/o port 1 input ani0 to ani7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. note 2 p20 input si1 p21 so1 p22 sck1 p23 stb/txd1 p24 busy/rxd1 p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 input to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 notes 1. when the p07/xt1 pin is used as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1 (do not use the feedback resistor incorporated in the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, set port 1 to the input mode. in this case, any connected on-chip pull-up resistors are automatically disabled. i/o port 2 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. chapter 3 pin functions ( pd780058 subseries) 3.1 pin function list (1) port pins (1/2) i/o 7-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. i/o port 3 8-bit i/o port input/output can be specified in 1-it units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 52 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud (1) port pins (2/2) pin name i/o function after reset alternate function p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 8-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. the test input flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p60 input p61 p62 p63 p64 rd p65 wr p66 wait p67 astb p70 input si2/rxd0 p71 so2/txd0 p72 sck2/asck p120 to p127 i/o port 12 input rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p130 to p131 i/o port 13 input ano0 to ano1 2-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. i/o port 7 3-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. if used as an input port, an on-chip pull-up resistor can be connected by setting software. i/o port 6 n-ch open-drain i/o port 8-bit i/o port on-chip pull-up resistors can be input/output can be specified in specified by mask option. 1-bit units. (mask rom version only). leds can be driven directly. 53 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 input input p00/ti00 intp1 p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 si0 input serial interface serial data input input p25/sb0 si1 p20 si2 p70/rxd so0 output serial interface serial data output input p26/sb1 so1 p21 so2 p71/txd sb0 p25/si0 sb1 p26/so0 sck0 serial interface serial clock input/output input p27 sck1 p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output input p23/txd1 busy input serial interface automatic transmit/receive busy input input p24/rxd1 rxd0 input asynchronous serial interface serial data input input p70/si2 rxd1 p24/busy txd0 output asynchronous serial interface serial data output input p71/so2 txd1 p23/stb asck input asynchronous serial interface serial clock input input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer (tm0) output (also used for 14-bit pwm output) input p30 to1 p31 to2 p32 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port outputting data in synchronization with trigger input p120 to p127 8-bit timer (tm1) output 8-bit timer (tm2) output serial interface serial data input/output input external interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). i/o i/o 54 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud (2) non-port pins (2/2) pin name i/o function after reset alternate function ad0 to ad7 i/o lower address/data bus when expanding memory externally input p40 to p47 a8 to a15 output higher address bus when expanding memory externally input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation to external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information output to ports 4 input p67 and 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input (also functions as analog power supply) av ref1 input d/a converter reference voltage input av ss a/d converter, d/a converter ground potential. use the same potential as v ss0 . reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation input p07 xt2 v dd0 positive power supply for ports v ss0 ground potential for ports v dd1 positive power supply (except ports and analog block) v ss1 ground potential (except ports and analog block) v pp high-voltage application for program write/verify. ic internally connected. connect directly to v ss0. 55 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2 description of pin functions 3.2.1 p00 to p05, p07 (port 0) p00 to p05 and p07 function as a 7-bit i/o port. besides serving as i/o port pins, they also function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. the following operating modes can be specified in 1-bit units. (1) port mode p00 and p07 function as input-only port pins and p01 to p05 function as i/o port pins. p01 to p05 can be specified as input or output in 1-bit units using port mode register 0 (pm0). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode in this mode, p00 to p05 and p07 function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp5 intp0 to intp5 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). intp0 or intp1 become 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (b) ti00 this is a pin for inputting the external count clock to the 16-bit timer/event counter. (c) ti01 this is a pin for inputting the capture trigger signal to the capture register (cr00) of the 16-bit timer/event counter. (d) xt1 this is a crystal connection pin for subsystem clock oscillation. 3.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an a/d converter analog inputs. the following operating modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 1 (pm1). when they are used as input port pins, on-chip pull-up resistor can be connected to them using pull-up resistor option register l (puol). (2) control mode p10 to p17 function as a/d converter analog input pins (ani0 to ani7). on-chip pull-up resistors are automatically disabled when these pins are specified as analog inputs. 56 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as data input/output to/from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output. the following operating modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 2 (pm2). when they are used as input ports, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p20 to p27 function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) si0, si1, so0, so1 these are serial data i/o pins of the serial interface. (b) sck0, sck1 these are serial clock i/o pins of the serial interface. (c) sb0, sb1 these are nec electronics standard serial bus interface i/o pins. (d) busy this is an automatic transmit/receive busy input pin of the serial interface. (e) stb this is an automatic transmit/receive strobe output pin of the serial interface. (f) rxd1, txd1 these are serial interface serial data i/o pins of the asynchronous serial interface. caution when p20 to p27 are used as serial interface pins, the i/o and output latches must be set according to the function the user requires. for the setting, see figure 16-4 format of serial operation mode register 0, figure 18-3 format of serial operation mode register 1, and table 19-2 serial interface channel 2 operating mode settings. 57 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2.4 p30 to p37 (port 3) p30 to p37 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as timer input/output, clock output and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode p30 to p37 function as an 8-bit i/o port. they can be specified as an input or output in 1-bit units using port mode register 3 (pm3). when they are used as input port pins, on-chip pull-up resistors can be connected to then using pull-up resistor option register l (puol). (2) control mode p30 to p37 function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 these are pins for inputting the external count clock to the 8-bit timer/event counter. (b) to0 to to2 these are timer output pins. (c) pcl this is a clock output pin. (d) buz this is a buzzer output pin. 3.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an address/data bus. the test input flag (krif) can be set to 1 by detecting a falling edge. the following operating modes can be specified in 8-bit units. (1) port mode p40 to p47 using function as an 8-bit i/o port. they can be specified for as input or output in 8-bit units using the internal memory expansion mode register (mm). when they are used as an input port pins, on-chip pull- up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p40 to p47 function as the lower address/data bus pins (ad0 to ad7) in external memory expansion mode. when these pins are used as an address/data bus, on-chip pull-up resistors are automatically disabled. 58 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an address bus. p50 to p57 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode p50 to p57 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 5 (pm5). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p50 to p57 function as the higher address bus pins (a8 to a15) in external memory expansion mode. when these pins are used as an address bus, on-chip pull-up resistors are automatically disabled. 3.2.7 p60 to p67 (port 6) p60 to p67 function as an 8-bit i/o port. besides serving as i/o port pins, they are also used for control in external memory expansion mode. p60 to p63 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode p60 to p67 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 6 (pm6). p60 to p63 are n-ch open-drain outputs. in mask rom products, on-chip pull-up resistors can be connected to these pins using a mask option. when p64 to p67 are used as input port pins, on-chip pull-up resistor can be connected using pull-up resistor option register l (puol). (2) control mode p60 to p67 function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when pins are used as control signal outputs, on-chip pull-up resistors are automatically disabled. caution when an external wait is not used in external memory expansion mode, p66 can be used as an i/o port pins. 59 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2.8 p70 to p72 (port 7) p70 to p72 function as a 3-bit i/o port. besides serving as i/o port pins, they also function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode p70 to p72 function as a 3-bit i/o port. they can be specified as input port or output in 1-bit units using port mode register 7 (pm7). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p70 to p72 function as serial interface data i/o and clock i/o. (a) si2, so2 these are serial data i/o pins of the serial interface. (b) sck2 this is a serial clock i/o pin of the serial interface. (c) rxd0, txd0 these are serial data i/o pins of the asynchronous serial interface. (d) asck this is a serial clock i/o pin of the asynchronous serial interface. caution when p70 to p72 are used as serial interface pins, the i/o and output latches must be set according to the function the user requires. for the setting, see the operation mode setting list in table 19-2 serial interface channel 2. 3.2.9 p120 to p127 (port 12) p120 to p127 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as a real-time output port. the following operating modes can be specified in 1-bit units. (1) port mode p120 to p127 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 12 (pm12). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register h (puoh). (2) control mode p120 to p127 function as a real-time output port (rtp0 to rtp7) that outputs data in synchronization with a trigger. 60 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.2.10 p130 and p131 (port 13) p130 and p131 function as a 2-bit i/o port. besides serving as i/o port pins, they also function as d/a converter analog output. the following operating modes can be specified in 1-bit units. (1) port mode p130 and p131 function as a 2-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 13 (pm13). when they are used as an input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register h (puoh). (2) control mode p130 and p131 function as d/a converter analog outputs (ano0 and ano1). caution when only one of the d/a converter channels is used with av ref1 < v dd0 , the other pins that are not used as analog outputs must be set as follows: set the pm13x bit of port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss0 . clear the pm13x bit of port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. 3.2.11 av ref0 this is the a/d converter reference voltage input pin. this pin also serves as an analog power supply pin. supply power to this pin when the a/d converter is used. when the a/d converter is not used, use the same voltage that of the v dd0 or v ss0 pin. 3.2.12 av ref1 this is the d/a converter reference voltage input pin. when the d/a converter is not used, use the same voltage that of the v dd0 pin. 3.2.13 av ss this is the ground voltage pin of a/d converter and d/a converter. always use the same voltage as that of the v ss0 pin even when the a/d converter or d/a converter is not used. 3.2.14 reset this is the low-level active system reset input pin. 3.2.15 x1 and x2 these are crystal resonator connection pins for main system clock oscillation. for external clock supply, input a signal to x1 and its inverted signal to x2. 3.2.16 xt1 and xt2 these are crystal resonator connection pins for subsystem clock oscillation. for external clock supply, input a signal to xt1 and its inverted signal to xt2. 3.2.17 v dd0 , v dd1 v dd0 is the positive power supply pin for ports. v dd1 is the positive power supply pin for blocks other than port and analog blocks. 61 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud v ss0 ic as short as possible 3.2.18 v ss0 , v ss1 v ss0 is the ground potential pin for ports. v ss1 is the ground potential pin for blocks other than port and analog blocks. 3.2.19 v pp (flash memory version only) this is the high-voltage application pin for flash memory programming mode setting and program write/verify. connect this pin in either of the following ways. connect independently to a 10 k ? pull-down resistor. by using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to v ss0 in the normal operation mode. 3.2.20 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780058 subseries at delivery. connect it directly to v ss0 with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss0 pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user s program may not run normally. connect the ic pin to v ss0 directly. 62 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud 3.3 i/o circuits and recommended connection of unused pins table 3-1 shows the pin i/o circuit types and the recommended connection of unused pins. refer to figure 3-1 for the configuration of the i/o circuit of each type. table 3-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0/ti00 2 input connect to v ss0 . p01/intp1/ti01 8-c i/o input: independently connect to v ss0 via a resistor. p02/intp2 output: leave open. p03/intp3 p04/intp4 p05/intp5 p07/xt1 16 input connect to v dd0 . p10/ani0 to p17/ani7 11-d i/o input: independently connect to v dd0 or v ss0 via a resistor. p20/si1 8-c output: leave open. p21/so1 5-h p22/sck1 8-c p23/stb/txd1 5-h p24/busy/rxd1 8-c p25/si0/sb0 10-b p26/so0/sb1 p27/sck0 p30/to0 5-h p31/to1 p32/to2 p33/ti1 8-c p34/ti2 p35/pcl 5-h p36/buz p37 p40/ad0 to p47/ad7 5-n i/o input: independently connect to v dd0 via a resistor. output: leave open. p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 or v ss0 via a resistor. output: leave open. 63 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud table 3-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p60 to p63 (mask rom version) 13-j i/o input: independently connect to v dd0 via a resistor. p60 to p63 (flash memory version) 13-k output: set 0 to the port and leave open at low level output. p64/rd 5-h i/o input: independently connect to v dd0 or v ss0 via a resistor. p65/wr output: leave open. p66/wait p67/astb p70/si2/rxd0 8-c p71/so2/txd0 5-h p72/sck2/asck 8-c p120/rtp0 to p127/rtp7 5-h p130/ano0, p131/ano1 12-c i/o input: independently connect to v ss0 via a resistor. output: leave open. reset 2 input xt2 16 leave open. av ref0 connect to v dd0 or v ss0 . av ref1 connect to v dd0 . av ss connect to v ss0 . ic (mask rom version) connect directly to v ss0 . v pp (flash memory version) independently connect via a 10 k ? pull-down resistor, or connect to v ss0 or v ss1 directly. 64 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud in pull-up enable v dd0 p-ch in/out input enable output disable data v dd0 p-ch n-ch type 2 type 5-h schmitt-triggered input with hysteresis characteristics type 5-n type 11-d type 10-b type 8-c pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out open drain output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + v ss0 v ss0 v ss0 v ss0 v ss0 v ss0 figure 3-1. pin i/o circuit list (1/2) 65 chapter 3 pin functions ( pd780058 subseries) user's manual u12013ej3v2ud type 12-c type 13-j type 13-k output disable v dd0 n-ch in/out rd medium breakdown input buffer data p-ch xt2 xt1 feedback cut-off p-ch type 16 output disable v dd0 v dd0 n-ch mask option in/out rd medium breakdown input buffer data p-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch input enable p-ch n-ch analog output voltage v ss0 v ss0 v ss0 figure 3-1. pin i/o circuit list (2/2) 66 user's manual u12013ej3v2ud pin name i/o function after reset alternate function p00 input port 0 input only input intp0/ti00 p01 intp1/ti01 p02 intp2 p03 intp3 p04 intp4 p05 intp5 p07 note 1 input input only input xt1 p10 to p17 i/o port 1 input ani0 to ani7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software note 2 . p20 si1 p21 so1 p22 sck1 p23 stb/txd1 p24 busy/rxd1 p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 input to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 notes 1. when the p07/xt1 pin is used as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1 (do not use the feedback resistor incorporated in the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, set port 1 to the input mode. in this case, any connected on-chip pull-up resistors are automatically disabled. i/o port 3 8-bit i/o port input/output mode can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. chapter 4 pin functions ( pd780058y subseries) 4.1 pin function list (1) port pins (1/2) i/o 7-bit i/o port input/output can be specified in 1-bit input units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. i/o port 2 input 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 67 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud (1) port pins (2/2) pin name i/o function after reset alternate function p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output can be specified in 8-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. the test input flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p60 p61 p62 p63 p64 rd p65 wr p66 wait p67 astb p70 si2/rxd0 p71 so2/txd0 p72 sck2/asck p120 to p127 i/o port 12 input rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p130 to p131 i/o port 13 input ano0 to ano1 2-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. i/o port 6 n-ch open-drain i/o port input 8-bit i/o port on-chip pull-up resistors can be input/output can be specified in specified by mask option. 1-bit units. (mask rom version only). leds can be driven directly. i/o port 7 input 3-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 68 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 input input p00/ti00 intp1 p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 si0 input serial interface serial data input input p25/sb0/sda0 si1 p20 si2 p70/rxd so0 output serial interface serial data output input p26/sb1/sda1 so1 p21 so2 p71/txd sb0 serial interface serial data input/output input p25/si0/sda0 sb1 p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 serial interface serial clock input/output input p27/scl sck1 p22 sck2 p72/asck scl p27/sck0 stb output serial interface automatic transmit/receive strobe output input p23/txd1 busy input serial interface automatic transmit/receive busy input input p24/rxd1 rxd0 input asynchronous serial interface serial data input input p70/si2 rxd1 p24/busy txd output asynchronous serial interface serial data output input p71/so2 txd1 p23/stb asck input asynchronous serial interface serial clock input input p72/sck2 ti00 external count clock input to 16-bit timer (tm0) p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer (tm0) output (also used for 14-bit pwm output) input p30 to1 p31 to2 p32 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port outputting data in synchronization with trigger input p120 to p127 input input 8-bit timer (tm1) output 8-bit timer (tm2) output external interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). i/o i/o 69 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud (2) non-port pins (2/2) pin name i/o function after reset alternate function ad0 to ad7 i/o lower address/data bus when expanding memory externally input p40 to p47 a8 to a15 output higher address bus when expanding memory externally input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation to external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information output to ports 4 input p67 and 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input (also functions as analog power supply) av ref1 input d/a converter reference voltage input av ss a/d converter, d/a converter ground potential. use the same potential as v ss0 . reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation input p07 xt2 v dd0 positive power supply for ports v ss0 ground potential for ports v dd1 positive power supply (except ports and analog block) v ss1 ground potential (except ports and analog block) v pp high-voltage application for program write/verify. v ss ground potential ic internally connected. connect directly to v ss0. 70 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2 description of pin functions 4.2.1 p00 to p05, p07 (port 0) p00 to p05 and p07 function as a 7-bit i/o port. besides serving as i/o port pins, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. the following operating modes can be specified in 1-bit units. (1) port mode p00 and p07 function as input-only port pins and p01 to p05 function as i/o port pins. p01 to p05 can be specified as input or output in 1-bit units using port mode register 0 (pm0). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode in this mode, p00 to p05 and p07 function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp5 intp0 to intp5 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). intp0 and intp1 become a 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (b) ti00 this is a pin for inputting the external count clock to the 16-bit timer/event counter. (c) ti01 this is a pin for inputting the capture trigger signal to the capture register (cr00) of the 16-bit timer/event counter. (d) xt1 this is a crystal connection pin for subsystem clock oscillation. 71 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an a/d converter analog inputs. the following operating modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 1 (pm1). when they are used as input port pins, on-chip pull-up resistor can be connected to them using pull-up resistor option register l (puol). (2) control mode p10 to p17 function as a/d converter analog input pins (ani0 to ani7). on-chip pull-up resistors are automatically disabled when these pins are specified as analog inputs. 4.2.3 p20 to p27 (port 2) p20 to p27 an 8-bit i/o port. besides serving as i/o port pins, they also function as data input/output to/from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output. the following operating modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 2 (pm2). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p20 to p27 function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) si0, si1, so0, so1, sb0, sb1, sda0, sda1 these are serial data i/o pins of the serial interface. (b) sck0, sck1, scl these are serial clock i/o pins of the serial interface. (c) busy this is an automatic transmit/receive busy input pin of the serial interface. (d) stb this is an automatic transmit/receive strobe output pin of the serial interface. (e) rxd1, txd1 these are serial interface serial data i/o pins of the asynchronous serial interface. caution when p20 to p27 are used as a serial interface pins, the i/o and output latches must be set according to the function the user requires. for the setting, see figure 17-4 format of serial operation mode register 0, figure 18-3 format of serial operation mode register 1, and table 19-2 serial interface channel 2 operating mode settings. 72 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.4 p30 to p37 (port 3) p30 to p37 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as timer input/output, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode p30 to p37 function as an 8-bit i/o port. they can be specified as an input or output using in 1-bit units port mode register 3 (pm3). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p30 to p37 function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 these are pins for inputting the external count clock to the 8-bit timer/event counter. (b) to0 to to2 these are timer output pins. (c) pcl this is a clock output pin. (d) buz this is a buzzer output pin. 73 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an address/data bus. the test input flag (krif) can be set to 1 by detecting a falling edge. the following operating modes can be specified in 8-bit units. (1) port mode p40 to p47 function as an 8-bit i/o port. they can be specified as input or output in 8-bit units using the internal memory expansion mode register (mm). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p40 to p47 function as the lower address/data bus pins (ad0 to ad7) in external memory expansion mode. when these pins are used as an address/data bus, on-chip pull-up resistors are automatically disabled. 4.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. besides serving as i/o port pins, they also function as an address bus. p50 to p57 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode p50 to p57 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 5 (pm5). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p50 to p57 function as the higher address bus pins (a8 to a15) in external memory expansion mode. when these pins are used as an address bus, on-chip pull-up resistors are automatically disabled. 4.2.7 p60 to p67 (port 6) p60 to p67 function as an 8-bit i/o port. besides serving as i/o port pins, they are also used for control in external memory expansion mode. p60 to p63 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode p60 to p67 function as an 8-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 6 (pm6). p60 to p63 are n-ch open-drain outputs. in mask rom products, on-chip pull-up resistors can be connected to these pins using a mask option. when p64 to p67 are used as input port pins, on-chip pull-up resistor can be connected using pull-up resistor option register l (puol). (2) control mode p60 to p67 functions as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when pins are used as control signal outputs, the on-chip pull-up resistors are automatically disabled. caution when an external wait is not used in external memory expansion mode, p66 can be used as an i/o port pin. 74 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.8 p70 to p72 (port 7) p70 to p72 function as a 3-bit i/o port. besides serving as i/o port pins, they also function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode p70 to p72 function as a 3-bit i/o port. they can be specified as input port or output in 1-bit units using port mode register 7 (pm7). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register l (puol). (2) control mode p70 to p72 function as serial interface data i/o and clock i/o. (a) si2, so2 these are serial data i/o pins of the serial interface. (b) sck2 this is a serial clock i/o pin of the serial interface. (c) rxd0, txd0 these are serial interface serial data i/o pins of the asynchronous serial interface. (d) asck this is a serial clock i/o pin of the asynchronous serial interface. caution when p70 to p72 are used as serial interface pins, the i/o and output latches must be set according to the function the user requires. for the setting, see to the operation mode setting list in table 19-2 serial interface channel 2. 4.2.9 p120 to p127 (port 12) p120 to p127 function as an 8-bit i/o port. besides serving as an i/o port pins, they also function as a real-time output port. the following operating modes can be specified in 1-bit units. (1) port mode p120 to p127 function as an 8-bit i/o port. they can be specified as input or output port in 1-bit units using port mode register 12 (pm12). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register h (puoh). (2) control mode p120 to p127 function as a real-time output port (rtp0 to rtp7) that outputs data in synchronization with a trigger. 75 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.10 p130 and p131 (port 13) p130 and p131 function as a 2-bit i/o port. besides serving as i/o port pins, they also function as d/a converter analog output. the following operating modes can be specified in 1-bit units. (1) port mode p130 and p131 function as a 2-bit i/o port. they can be specified as input or output in 1-bit units using port mode register 13 (pm13). when they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register h (puoh). (2) control mode p130 and p131 function as d/a converter analog outputs (ano0 and ano1). caution when only one of the d/a converter channels is used with av ref1 < v dd0 , the other pins that are not used as analog outputs must be set as follows: set the pm13x bit of port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss0 . clear the pm13x bit of port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. 4.2.11 av ref0 this is the a/d converter reference voltage input pin. this pin also serves as an analog power supply pin. supply power to this pin when the a/d converter is used. when the a/d converter is not used, use the same voltage that of the v dd0 or v ss0 pin. 4.2.12 av ref1 this is the d/a converter reference voltage input pin. when the d/a converter is not used, use the same voltage that of the v dd0 pin. 4.2.13 av ss this is the ground voltage pin of a/d converter and d/a converter. always use the same voltage as that of the v ss0 pin even when the a/d converter or d/a converter is not used. 4.2.14 reset this is the low-level active system reset input pin. 4.2.15 x1 and x2 these are crystal resonator connection pins for main system clock oscillation. for external clock supply, input a signal to x1 and its inverted signal to x2. 4.2.16 xt1 and xt2 these are crystal resonator connection pins for subsystem clock oscillation. for external clock supply, input a signal to xt1 and its inverted signal to xt2. 4.2.17 v dd0 , v dd1 v dd0 is the positive power supply pin for ports. v dd1 is the positive power supply pin for blocks other than port and analog blocks. 76 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.2.18 v ss0 , v ss1 v ss0 is the ground potential pin for ports. v ss1 is the ground potential pin for blocks other than port and analog blocks. 4.2.19 v pp (flash memory version only) this is the high-voltage apply pin for flash memory programming mode setting and program write/verify. connect this pin in either of the following ways. connect independently to a 10 k ? pull-down resistor. by using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to v ss0 in the normal operation mode. 4.2.20 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780058y subseries at delivery. connect it directly to v ss0 with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss0 pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user? program may not run normally. connect the ic pin to v ss0 directly. v ss0 ic as short as possible 77 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud 4.3 i/o circuits and recommended connection of unused pins table 4-1 shows the pin i/o circuit types and the recommended connection of unused pins. refer to figure 4-1 for the configuration of the i/o circuit of each type. table 4-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0/ti00 2 input connect to v ss0 . p01/intp1/ti01 8-c i/o input: independently connect to v ss0 via a resistor . p02/intp2 output: leave open. p03/intp3 p04/intp4 p05/intp5 p07/xt1 16 input connect to v dd0 p10/ani0 to p17/ani7 11-d i/o input: independently connect to v dd0 or v ss0 via a resistor. p20/si1 8-c output: leave open. p21/so1 5-h p22/sck1 8-c p23/stb/txd1 5-h p24/busy/rxd1 8-c p25/si0/sb0/sda0 10-b p26/so0/sb1/sda1 p27/sck0/scl p30/to0 5-h p31/to1 p32/to2 p33/ti1 8-c p34/ti2 p35/pcl 5-h p36/buz p37 p40/ad0 to p47/ad7 5-n i/o input: independently connect to v dd0 via a resistor. output: leave open. p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 or v ss0 via a resistor. output: leave open. 78 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud table 4-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p60 to p63 (mask rom version) 13-j i/o input: independently connect to v dd0 via a resistor. output: set 0 to the port and leave open at low level output. p60 to p63 (flash memory version) 13-k i/o input: independently connect to v dd0 or v ss0 via a resistor. p64/rd 5-h output: leave open. p65/wr p66/wait p67/astb p70/si2/rxd0 8-c p71/so2/txd0 5-h p72/sck2/asck 8-c p120/rtp0 to p127/rtp7 5-h p130/ano0, p131/ano1 12-c i/o input: independently connect to v ss0 via a resistor. output: leave open. reset 2 input xt2 16 leave open. av ref0 connect to v dd0 or v ss0 . av ref1 connect to v dd0 . av ss connect to v ss0 . ic (mask rom version) connect directly to v ss0 . v pp (flash memory version) independently connect 10 k ? pull-down resistor, or connect to v ss0 or v ss1 directly. 79 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud figure 4-1. pin i/o circuit list (1/2) in pull-up enable v dd0 p-ch in/out input enable output disable data v dd0 p-ch n-ch type 2 type 5-h schmitt-triggered input with hysteresis characteristics type 5-n type 11-d type 10-b type 8-c pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out open drain output disable data v dd0 p-ch n-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + v ss0 v ss0 v ss0 v ss0 v ss0 v ss0 80 chapter 4 pin functions ( pd780058y subseries) user's manual u12013ej3v2ud figure 4-1. pin i/o circuit list (2/2) type 12-c type 13-j type 13-k output disable v dd0 n-ch in/out rd medium breakdown input buffer data p-ch xt2 xt1 feedback cut-off p-ch type 16 output disable v dd0 v dd0 n-ch mask option in/out rd medium breakdown input buffer data p-ch pull-up enable v dd0 p-ch in/out output disable data v dd0 p-ch n-ch input enable p-ch n-ch analog output voltage v ss0 v ss0 v ss0 81 user's manual u12013ej3v2ud chapter 5 cpu architecture 5.1 memory spaces figures 5-1 to 5-6 show the memory maps. figure 5-1. memory map ( pd780053, 780053(a), 780053y, 780053y(a)) 0000h data memory space general-purpose registers 32 8 bits internal rom 24,576 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits external memory 39,552 8 bits unusable program memory space 6000h 5fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits unusable fb00h faffh 82 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-2. memory map ( pd780054, 780054(a), 780054y, 780054y(a)) 0000h data memory space general-purpose registers 32 8 bits internal rom 32,768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits external memory 31,360 8 bits unusable program memory space 8000h 7fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits unusable fb00h faffh 83 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-3. memory map ( pd780055, 780055(a), 780055y, 780055y(a)) 0000h data memory space general-purpose registers 32 8 bits internal rom 40,960 8 bits 9fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits external memory 23,168 8 bits unusable program memory space a000h 9fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits unusable fb00h faffh 84 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-4. memory map ( pd780056, 780056(a), 780056y, 780056y(a)) 0000h data memory space general-purpose registers 32 8 bits internal rom 49,152 8 bits bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits external memory 14,976 8 bits unusable program memory space c000h bfffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits unusable fb00h faffh 85 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-5. memory map ( pd780058, 780058b, 780058b(a), 780058by, 780058by(a)) note when the internal rom size is 60 kb, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to 56 kb or less using the internal memory size switching register (ims). 0000h data memory space general-purpose registers 32 8 bits internal rom 61,440 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits unusable note unusable program memory space f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits internal expansion ram 1,024 8 bits f400h f3ffh unusable fb00h faffh 86 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-6. memory map ( pd78f0058, 78f0058y) note when the flash memory size is 60 kb, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the flash memory size to 56 kb or less using the internal memory size switching register (ims). 0000h data memory space general-purpose registers 32 8 bits flash memory 61,440 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 8 bits unusable program memory space f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits special function registers (sfrs) 256 8 bits internal expansion ram 1,024 8 bits f400h f3ffh unusable fb00h faffh unusable note 87 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.1.1 internal program memory space the pd780058 and 780058y subseries have various sizes of internal rom or flash memory as shown below. the internal program memory space stores programs and table data. normally, they are addressed with a program counter (pc). part number internal rom type capacity pd780053, 780053(a), 780053y, 780053y(a) mask rom 24,576 8 bits pd780054, 780054(a), 780054y, 780054y(a) 32,768 8 bits pd780055, 780055(a), 780055y, 780055y(a) 40,960 8 bits pd780056, 780056(a), 780056y, 780056y(a) 49,152 8 bits pd780058, 780058b, 780058b(a), 780058by, 780058by(a) 61,440 8 bits pd78f0058, 78f0058y flash memory 61,440 8 bits the internal program memory is divided into the following three areas. 88 chapter 5 cpu architecture user's manual u12013ej3v2ud (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the program start addresses for branch upon reset input interrupt request or generation are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. table 5-1. vector table vector table address interrupt source 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intp4 0010h intp5 0014h intcsi0 0016h intcsi1 0018h intser 001ah intsr/intcsi2 001ch intst 001eh inttm3 0020h inttm00 0022h inttm01 0024h inttm1 0026h inttm2 0028h intad 003eh brk (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 89 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.1.2 internal data memory space the pd780058 and 780058y subseries incorporate the following rams. (1) internal high-speed ram high-speed memory of the following configuration is incorporated: 1,024 8 bits (fb00h to feffh) in this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated to the 32-byte area fee0h to feffh. the internal high-speed ram can also be used as a stack memory area. (2) internal buffer ram buffer ram is allocated to the 32-byte area from fac0h to fadfh. the internal buffer ram is used to store transmit/receive data of serial interface channel 1 (in 3-wire serial i/o mode with automatic transmit/receive function). if the 3-wire serial i/o mode with automatic transmit/receive function is not used, the internal buffer ram can also be used as normal ram. (3) internal expansion ram ( pd780058, 780058b, 780058b(a), 780058by, 780058by(a), 78f0058, 78f0058y only) internal expansion ram is allocated to the 1,024-byte area from f400h to f7ffh. 5.1.3 special function register (sfr) area on-chip peripheral hardware special-function registers (sfrs) are allocated to the area ff00h to ffffh. (see table 5-2 special-function register list in 5.2.3 special function registers (sfrs) ). caution do not access addresses where sfrs are not assigned. 5.1.4 external memory space the external memory space is accessible by setting the internal memory expansion mode register (mm). external memory space can store program, table data, etc. and allocate peripheral devices. 5.1.5 data memory addressing the method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. the address of the instruction to be executed next is addressed by the program counter pc (for details, see 5.3 instruction address addressing ). to address the memory that is manipulated when an instruction is executed, the pd780058, 780058y subseries is provided with many addressing modes with a high operability. especially at addresses corresponding to data memory area, particular addressing modes can be used in accordance with the functions of the special function registers (sfrs) and general-purpose registers. this area is between fb00h and ffffh. the data memory space is the entire 64 kb space (0000h to ffffh). figures 5-7 to 5-12 show the data memory addressing modes. for details of each addressing, see 5.4 operand address addressing. 90 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-7. data memory addressing ( pd780053, 780053(a), 780053y, 780053y(a)) 0000h general-purpose registers 32 8 bits internal rom 24,576 8 bits internal buffer ram 32 8 bits external memory 39,552 8 bits unusable 6000h 5fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 91 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-8. data memory addressing ( pd780054, 780054(a), 780054y, 780054y(a)) 0000h general-purpose registers 32 8 bits internal rom 32,768 8 bits internal buffer ram 32 8 bits external memory 31,360 8 bits unusable 8000h 7fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 92 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-9. data memory addressing ( pd780055, 780055(a), 780055y, 780055y(a)) 0000h general-purpose registers 32 8 bits internal rom 40,960 8 bits internal buffer ram 32 8 bits external memory 23,168 8 bits unusable a000h 9fffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 93 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-10. data memory addressing ( pd780056, 780056(a), 780056y, 780056y(a)) 0000h general-purpose registers 32 8 bits internal rom 49,152 8 bits internal buffer ram 32 8 bits external memory 14,976 8 bits unusable c000h bfffh fa80h fa7fh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 94 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-11. data memory addressing ( pd780058, 780058b, 780058b(a), 780058by, 780058by(a)) note when the internal rom size is 60 kb, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to 56 kb or less using the internal memory size switching register (ims). 0000h general-purpose registers 32 8 bits internal rom 61,440 8 bits internal buffer ram 32 8 bits unusable f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh f400h f3ffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits internal expansion ram 1,024 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing unusable note 95 chapter 5 cpu architecture user's manual u12013ej3v2ud figure 5-12. data memory addressing ( pd78f0058, 78f0058y) note when the flash memory size is 60 kb, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the flash memory size to 56 kb or less using the internal memory size switching register (ims). 0000h general-purpose registers 32 8 bits flash memory 61,440 8 bits internal buffer ram 32 8 bits unusable f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1,024 8 bits unusable fb00h faffh f400h f3ffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits internal expansion ram 1,024 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing unusable note 96 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.2 processor registers the pd780058 and 780058y subseries incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-13. program counter format (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti, and pop psw instructions. reset input sets the psw to 02h. figure 5-14. program status word format 15 0 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pc 70 ie psw z rbs1 ac rbs0 0 isp cy 97 chapter 5 cpu architecture user's manual u12013ej3v2ud (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgment operations of the cpu. when ie = 0, all interrupt requests except the non-maskable interrupt are disabled (di status). when ie = 1, interrupts are enabled (ei status). at this time, acknowledgment of interrupts is controlled with an inservice priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the interrupt enable flag is reset to 0 when the di instruction is executed or when an interrupt request is acknowledged, and set to 1 when the ei instruction is executed. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored in these flags. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when isp = 0, the vectored interrupt whose priority is specified by the priority specification flag registers (pr0l, pr0h, and pr1l) (see 21.3 (3) priority specification flag registers (pr0l, pr0h, and pr1l) ) to be low is disabled. whether the interrupt is actually acknowledged is controlled by the status of the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 98 chapter 5 cpu architecture user's manual u12013ej3v2ud (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area (fb00h to feffh) can be set as the stack area. figure 5-15. stack pointer format the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 5-16 and 5-17. caution because reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 5-16. data to be saved to stack memory figure 5-17. data to be reset from stack memory 15 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sp interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 99 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.2.2 general registers general-purpose registers are mapped at particular addresses (fee0h to feffh) of the data memory. they consist of 4 banks, each bank containing eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register and two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt requests for each bank. figure 5-18. general-purpose register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 100 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.2.3 special-function registers (sfrs) unlike a general-purpose register, each special-function register has a special function. these registers are allocated in the ff00h to ffffh area. special-function registers can be manipulated like general-purpose registers, with operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the special-function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified using an address. 8-bit manipulation describe the symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified using an address. 16-bit manipulation describe the symbol reserved by assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-2 gives a list of special-function registers. the meanings of items in the table are as follows. symbol symbol indicating the addresses of the special function register. these symbols are reserved words in the ra78k0 and defined by header file sfrbit.h in the cc78k0, and can be used as the operands of instructions when the ra78k0, id78k0, id78k0-ns, and sm78k0 are used. r/w indicates whether the corresponding special-function register can be read or written. r/w: read/write enabled r: read only w: write only manipulatable bit units indicates the bit units (1, 8, or 16 bits) in which the register can be manipulated. ?indicates that the register cannot be manipulated in the indicated bit units. after reset indicates each register status upon reset input. 101 chapter 5 cpu architecture user's manual u12013ej3v2ud address special-function register (sfr) name symbol r/w after reset ff00h port 0 p0 r/w ? 00h ff01h port 1 p1 ? ff02h port 2 p2 ? ff03h port 3 p3 ? ff04h port 4 p4 ? undefined ff05h port 5 p5 ? ff06h port 6 p6 ? ff07h port 7 p7 ? 00h ff0ch port 12 p12 ? ff0dh port 13 p13 ? ff10h capture/compare register 00 cr00 undefined ff11h ff12h capture/compare register 01 cr01 ff13h ff14h 16-bit timer register tm0 r 0000h ff15h ff16h compare register 10 cr10 r/w undefined ff17h compare register 20 cr20 ff18h 8-bit timer register 1 tms tm1 r ? 00h ff19h 8-bit timer register 2 tm2 ff1ah serial i/o shift register 0 sio0 r/w undefined ff1bh serial i/o shift register 1 sio1 ff1fh a/d conversion result register adcr r ff20h port mode register 0 pm0 r/w ? ffh ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff25h port mode register 5 pm5 ? ff26h port mode register 6 pm6 ? ff27h port mode register 7 pm7 ? ff2ch port mode register 12 pm12 ? ff2dh port mode register 13 pm13 ? ff30h real-time output buffer register l rtbl 00h ff31h real-time output buffer register h rtbh ff34h real-time output port mode register rtpm ? ff36h real-time output port control register rtpc ? table 5-2. special-function register list (1/3) manipulatable bit unit 8 bits 1 bit 16 bits 102 chapter 5 cpu architecture user's manual u12013ej3v2ud address special-function register (sfr) name symbol r/w after reset ff38h correction address register 0 note corad0 r/w 0000h ff39h ff3ah correction address register 1 note corad1 ff3bh ff40h timer clock select register 0 tcl0 ? 00h ff41h timer clock select register 1 tcl1 ff42h timer clock select register 2 tcl2 ff43h timer clock select register 3 tcl3 88h ff47h sampling clock select register scs 00h ff48h 16-bit timer mode control register tmc0 ? ff49h 8-bit timer mode control register 1 tmc1 ? ff4ah watch timer mode control register tmc2 ? ff4ch capture/compare control register 0 crc0 ? 04h ff4eh 16-bit timer output control register toc0 ? 00h ff4fh 8-bit timer output control register toc1 ? ff60h serial operating mode register 0 csim0 ? ff61h serial bus interface control register sbic ? ff62h slave address register sva undefined ff63h interrupt timing specify register sint ? 00h ff68h serial operating mode register 1 csim1 ? ff69h automatic data transmit/receive control register adtc ? ff6ah automatic data transmit/receive address pointer adtp ff6bh automatic data transmit/receive interval specify register adti ? ff70h asynchronous serial interface mode register asim ? ff71h asynchronous serial interface status register asis r ? ff72h serial operating mode register 2 csim2 rw ? ff73h baud rate generator control register brgc ff74h transmit shift register txs sio2 w ffh receive buffer register rxb r ff75h serial interface pin select register sips r/w ? 00h ff80h a/d converter mode register adm ? 01h ff84h a/d converter input select register adis 00h ff8ah correction control register note corcn ? ff90h d/a conversion value setting register 0 dacs0 ff91h d/a conversion value setting register 1 dacs1 ff98h d/a converter mode register dam ? table 5-2. special-function register list (2/3) manipulatable bit unit 8 bits 1 bit 16 bits note this register is provided only in the pd780058, 780058b, 780058b(a), 780058by, 780058by(a), 78f0058, and 78f0058y. 103 chapter 5 cpu architecture user's manual u12013ej3v2ud if0 00h address special-function register (sfr) name symbol r/w after reset ffd0h to external access area note 1 r/w ? undefined ffdfh ffe0h interrupt request flag register 0l ? ffe1h interrupt request flag register 0h ? ffe2h interrupt request flag register 1l if1l ? ffe4h interrupt mask flag register 0l ? ffe5h interrupt mask flag register 0h ? ffe6h interrupt mask flag register 1l mk1l ? ffe8h priority order specification flag register 0l ? ffe9h priority order specification flag register 0h ? ffeah priority order specification flag register 1l pr1l ? ffech external interrupt mode register 0 intm0 ffedh external interrupt mode register 1 intm1 fff0h internal memory size switching register ims note 2 fff2h oscillation mode select register osms w fff3h pull-up resistor option register h puoh r/w ? fff4h internal expansion ram size ixs w 0ah switching register note 3 fff6h key return mode register krm ? 02h fff7h pull-up resistor option register l puol ? 00h fff8h memory expansion mode register mm ? 10h fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register osts fffbh processor clock control register pcc ? if0l if0h mk0l mk0h pr0l pr0h table 5-2. special-function register list (3/3) manipulatable bit unit 8 bits 1 bit 16 bits mk0 ffh pr0 00h 00h r/w 04h notes 1. the external access area cannot be accessed using sfr addressing. access the area using direct addressing. 2. the value after reset depends on the product. pd780053, 780053(a), 780053y, 780053y(a): c6h pd780054, 780054(a), 780054y, 780054y(a): c8h pd780055, 780055(a), 780055y, 780055y(a): cah pd780056, 780056(a), 780056y, 780056y(a): cch pd780058, 780058b, 780058b(a), 780058by, 780058by(a): cfh pd78f0058, 78f0058y: cfh 3. this register is provided only in the pd780058, 780058b, 780058b(a), 780058by, 780058by(a), 78f0058, and 78f0058y. 104 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.3 instruction address addressing the instruction address is determined by the program counter (pc) contents. the contents of the pc are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 instructions user? manual (u12326e) . 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two? complement data (?28 to +127) and bit 7 becomes a sign bit. in the relative addressing modes, execution branches in a relative range of ?28 to +127 from the first address of the next instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... 105 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. the call !addr16 and br !addr16 instructions can branch in the entire memory space. the callf !addr11 instruction branches to an area of addresses 0800h to 0fffh. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10 to 8 11 10 00001 643 callf fa 7 to 0 106 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.3.3 table indirect addressing [function] the table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. before the callt [addr5] instruction is executed, table indirect addressing is performed. this instruction references an address stored in the memory table at addresses 40h to 7fh, and can branch in the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 to 0 operation code 107 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.3.4 register addressing [function] the register pair (ax) contents to be specified by an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 108 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general-purpose register area is automatically (illicitly) addressed. in the pd780058 and 780058y subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu register a for multiplicand and ax register for product storage divuw register ax for dividend and quotient storage adjba/adjbs register a for storage of numeric values which become decimal correction targets ror4/rol4 register a for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of register a and register x is stored in ax. in this example, the a and ax registers are specified by implied addressing. 109 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.2 register addressing [function] this addressing accesses a general-purpose register as an operand. the general-purpose register accessed is specified by the register bank select flags (rbs0 and rbs1) and register specification code (rn or rpn) in an instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified by 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [description example] mov a, c; when selecting c register as r operation code 01100010 register specification code incw de; when selecting de register pair as rp operation code 10000100 register specification code 110 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.3 direct addressing [function] this addressing directly addresses the memory indicated by the immediate data in an instruction word. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 opcode addr16 (lower) addr16 (higher) 111 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this address is applied is a 256-byte space of addresses fe20h to ff1fh. an internal ram and special-function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) to which short direct addressing is applied is a part of the entire sfr area. ports frequently accessed by the program, and the compare registers and capture registers of timer/event counters are mapped to this area. these sfrs can be manipulated with a short byte length and few clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] on next page. [operand format] identifier description saddr label or immediate data of fe20h to ff1fh saddrp label or immediate data of fe20h to ff1fh (even address only) 112 chapter 5 cpu architecture user's manual u12013ej3v2ud [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 opcode saddr-offset 113 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.5 special-function register (sfr) addressing [function] the memory-mapped special-function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 opcode sfr-offset 1 114 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.6 register indirect addressing [function] this addressing addresses the memory with the contents of a register pair specified as an operand. the register pair to be accessed is specified by the register bank select flags (rbs0 and rbs1) and register pair specification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 15 0 8 d 7 e 0 7 7 0 a de memory contents of addressed memory are transferred. memory address specified by register pair de 115 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.7 based addressing [function] this addressing addresses the memory by adding 8-bit immediate data to the contents of the hl register pair which is used as a base register and by using the result of the addition. the hl register pair to be accessed is in the register bank specified by the register bank select flags (rbs0 and rbs1). the addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 116 chapter 5 cpu architecture user's manual u12013ej3v2ud 5.4.8 based indexed addressing [function] this addressing addresses the memory by adding the contents of the hl register, which is used as a base register, to the contents of the b or c register specified in the instruction word, and by using the result of the addition. the hl, b, and c registers to be accessed are registers in the register bank specified by the register bank select flags (rbs0 and rbs1). the addition is performed by extending the contents of the b or c register to 16 bits as a positive number. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing can be used to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101 117 user's manual u12013ej3v2ud chapter 6 port functions 6.1 port functions the pd780058 and 780058y subseries incorporate two input ports and sixty-six i/o ports. figure 6-1 shows the port types. every port can be manipulated in 1-bit and 8-bit units and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware i/o pins. figure 6-1. port types ? ? ? ? ? ? ? ? ? port 0 p00 p07 ? ? ? ? ? ? ? ? ? port 1 p10 p17 ? ? ? ? ? ? ? ? ? port 2 p20 p27 ? ? ? ? ? ? ? ? ? port 3 p30 p37 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 13 ? ? ? port 7 port 12 port 6 port 5 p50 p57 p60 p67 p70 p72 p120 p127 p130 p131 p05 ? ? ? ? ? ? ? ? ? port 4 p40 p47 118 chapter 6 port functions user's manual u12013ej3v2ud pin name function alternate function p00 port 0 input only intp0/ti00 p01 7-bit i/o port intp1/ti01 p02 intp2 p03 intp3 p04 intp4 p05 intp5 p07 input only xt1 p10 to p17 port 1 ani0 to ani7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p20 si1 p21 so1 p22 sck1 p23 stb/txd1 p24 busy/rxd1 p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 p40 to p47 port 4 ad0 to ad7 8-bit i/o port input/output can be specified i 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. the test input flag (krif) is set to 1 by falling edge detection. p50 to p57 port 5 a8 to a15 8-bit i/o port led can be driven directly. input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. table 6-1. port functions ( pd780058 subseries) (1/2) input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 2 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 3 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 119 chapter 6 port functions user's manual u12013ej3v2ud table 6-1. port functions ( pd780058 subseries) (2/2) pin name function alternate function p60 p61 p62 p63 p64 rd p65 wr p66 wait p67 astb p70 si2/rxd0 p71 so2/txd0 p72 sck2/asck p120 to p127 port 12 rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, on-chip pull-up resistor can be connected by setting software. p130 and p131 port 13 ano0, ano1 2-bit i/o port input/output can be specified in 1-bit units. if used as an input port, on-chip pull-up resistor can be connected by setting software. port 7 3-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. n-ch open-drain i/o port on-chip pull-up resistors can be specified by mask option. (mask rom version only). leds can be driven directly. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 6 8-bit i/o port input/output can be specified in 1-bit units. 120 chapter 6 port functions user's manual u12013ej3v2ud table 6-2. port functions ( pd780058y subseries) (1/2) pin name function alternate function p00 input only intp0/ti00 p01 intp1/ti01 p02 intp2 p03 intp3 p04 intp4 p05 intp5 p07 input only xt1 p10 to p17 port 1 ani0 to ani7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. p20 si1 p21 so1 p22 sck1 p23 stb/txd1 p24 busy/rxd1 p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 to0 p31 to1 p32 to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 p40 to p47 port 4 ad0 to ad7 8-bit i/o port input/output can be specified in 8-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. the test input flag (krif) is set to 1 by falling edge detection. p50 to p57 port 5 a8 to a15 8-bit i/o port leds can be driven directly. input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 0 7-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 2 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 3 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 121 chapter 6 port functions user's manual u12013ej3v2ud table 6-2. port functions ( pd780058y subseries) (2/2) pin name function alternate function p60 p61 p62 p63 p64 rd p65 wr p66 wait p67 astb p70 si2/rxd0 p71 so2/txd0 p72 sck2/asck p120 to p127 port 12 rtp0 to rtp7 8-bit i/o port input/output can be specified in 1-bit units. if used as an input port, on-chip pull-up resistor can be connected by setting software. p130 and p131 port 13 ano0, ano1 2-bit i/o port input/output mode can be specified in 1-bit units. if used as an input port, on-chip pull-up resistor can be connected by setting software. n-ch open-drain i/o port on-chip pull-up resistors can be specified by mask option. (mask rom version only). leds can be driven directly. if used as an input port, an on-chip pull-up resistor can be connected by setting software. port 6 8-bit i/o port input/output can be specified in 1-bit units. port 7 3-bit i/o port input/output can be specified in 1-bit units. if used as an input port, an on-chip pull-up resistor can be connected by setting software. 122 chapter 6 port functions user's manual u12013ej3v2ud 6.2 port configuration a port consists of the following hardware. table 6-3. port configuration item configuration control register port mode register (pmm: m = 0 to 3, 5 to 10, 12, 13) pull-up resistor option register (puoh, puol) memory expansion mode register (mm) note key return mode register (krm) port total: 68 (input: 2, i/o: 66) pull-up resistor mask rom version total: 66 (software specifiable: 62, mask option: 4) flash memory version total: 62 note mm specifies the input/output mode of port 4. 6.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. pins p01 to p05 can be set to input or output mode in 1-bit units using port mode register 0 (pm0). pins p00 and p07 are input-only ports. when pins p01 to p05 are used as input ports, an on-chip pull-up resistor can be connected to them in 6-bit units using pull-up resistor option register l (puol). alternate functions include external interrupt request input, external count clock input to the timer and crystal connection for subsystem clock oscillation. reset input sets port 0 to input mode. figures 6-2 and 6-3 show block diagrams of port 0. caution because port 0 also serves as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. 123 chapter 6 port functions user's manual u12013ej3v2ud figure 6-2. block diagram of p00 and p07 rd: port 0 read signal figure 6-3. block diagram of p01 to p05 puo: pull-up resistor option register pm: port mode register rd: port 0 read signal wr: port 0 write signal p00/intp0/ti00, p07/xt1 rd internal bus p-ch wr pm wr port rd wr puo v dd0 p01/intp1/ti01, p02/intp2 to p05/intp5 selector puo0 output latch (p01 to p05) pm01 to pm05 internal bus 124 chapter 6 port functions user's manual u12013ej3v2ud 6.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to input or output mode in 1-bit units using port mode register 1 (pm1). when pins p10 to p17 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). alternate functions include a/d converter analog input. reset input sets port 1 to input mode. figure 6-4 shows a block diagram of port 1. caution a pull-up resistor cannot be used for pins used as a/d converter analog inputs. figure 6-4. block diagram of p10 to p17 puo: pull-up resistor option register pm: port mode register rd: port 1 read signal wr: port 1 write signal p-ch wr pm wr port rd wr puo v dd0 p10/ani0 to p17/ani7 selector puo1 output latch (p10 to p17) pm10 to pm17 internal bus 125 chapter 6 port functions user's manual u12013ej3v2ud 6.2.3 port 2 ( pd780058 subseries) port 2 is an 8-bit i/o port with an output latch. pins p20 to p27 can be set to input or output mode in 1-bit units using port mode register 2 (pm2). when pins p20 to p27 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). alternate functions include serial interface data i/o, clock i/o, automatic transmit/receive busy input, and strobe output. reset input sets port 2 to input mode. figures 6-5 and 6-6 show a block diagram of port 2. cautions 1. when used as serial interface pins, set input/output and the output latch according to the function. for the setting method, see figure 16-4 format of serial operating mode register 0, figure 18-3 format of serial operating mode register 1, and table 19-2 serial interface channel 2 operating mode settings. 2. when reading the pin state in sbi mode, set the pm2n bit of pm2 to 1 (n = 5, 6) (see the description of (10) judging busy state of slave in section 16.4.3 sbi mode operation). figure 6-5. block diagram of p20, p21, and p23 to p26 puo: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo2 output latch (p20, p21, p23 to p26) pm20, pm21 pm23 to pm26 internal bus alternate function p20/si1, p21/so1, p23/stb/txd1, p24/busy/rxd1, p25/si0/sb0, p26/so0/sb1 126 chapter 6 port functions user's manual u12013ej3v2ud figure 6-6. block diagram of p22 and p27 puo: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo2 output latch (p22, p27) pm22, pm27 internal bus alternate function p22/sck1, p27/sck0 127 chapter 6 port functions user's manual u12013ej3v2ud 6.2.4 port 2 ( pd780058y subseries) port 2 is an 8-bit i/o port with an output latch. pins p20 to p27 can be set to input or output mode in 1-bit units using port mode register 2 (pm2). when pins p20 to p27 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). alternate functions include serial interface data i/o, clock i/o, automatic transmit/receive busy input, and strobe output. reset input sets port 2 to input mode. figures 6-7 and 6-8 show a block diagram of port 2. caution when used as serial interface pins, set input/output and the output latch according to the function. for the setting method, see figure 17-4 format of serial operating mode register 0, figure 18-3 format of serial operating mode register 1, and table 19-2 serial interface channel 2 operating mode settings. figure 6-7. block diagram of p20, p21, and p23 to p26 puo: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo2 output latch (p20, p21, p23 to p26) pm20, pm21 pm23 to pm26 internal bus alternate function p20/si1, p21/so1, p23/stb/txd1, p24/busy/rxd1, p25/si0/sb0/sda0, p26/so0/sb1/sda1 128 chapter 6 port functions user's manual u12013ej3v2ud figure 6-8. block diagram of p22 and p27 puo: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo2 output latch (p22 and p27) pm22, pm27 internal bus alternate function p22/sck1, p27/sck0/scl 129 chapter 6 port functions user's manual u12013ej3v2ud 6.2.5 port 3 port 3 is an 8-bit i/o port with an output latch. pins p30 to p37 can be set to input or output mode in 1-bit units using port mode register 3 (pm3). when pins p30 to p37 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). alternate functions include timer i/o, clock output and buzzer output. reset input sets port 3 to input mode. figure 6-9 shows a block diagram of port 3. figure 6-9. block diagram of p30 to p37 puo: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo3 output latch (p30 to p37) pm30 to pm37 internal bus alternate function p30/to0 to p32/to2, p33/ti1, p34/ti2, p35/pcl, p36/buz, p37 130 chapter 6 port functions user's manual u12013ej3v2ud 6.2.6 port 4 port 4 is an 8-bit i/o port with an output latch. pins p40 to p47 can be set to input or output mode in 8-bit units using the memory expansion mode register (mm). when pins p40 to p47 are used as an input port, an on-chip pull- up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). the test input flag (krif) can be set to 1 by detecting a falling edge. alternate functions include an address/data bus function in external memory expansion mode. reset input sets port 4 to input mode. figures 6-10 and 6-11 show a block diagram of port 4 and of the falling edge detector, respectively. figure 6-10. block diagram of p40 to p47 puo: pull-up resistor option register mm: memory expansion mode register rd: port 4 read signal wr: port 4 write signal figure 6-11. block diagram of falling edge detector p-ch wr mm wr port rd wr puo v dd0 selector puo4 output latch (p40 to p47) mm internal bus p40/ad0 to p47/ad7 p40 p41 p42 p43 p44 p45 p46 p47 falling edge detector krmk krif set signal standby release signal 131 chapter 6 port functions user's manual u12013ej3v2ud 6.2.7 port 5 port 5 is an 8-bit i/o port with an output latch. pins p50 to p57 can be set to input or output mode in 1-bit units using the port mode register 5 (pm5). when pins p50 to p57 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register l (puol). port 5 can drive leds directly. alternate functions include an address bus function in external memory expansion mode. reset input sets port 5 to input mode. figure 6-12 shows a block diagram of port 5. figure 6-12. block diagram of p50 to p57 puo: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo5 output latch (p50 to p57) pm50 to pm57 internal bus p50/a8 to p57/a15 132 chapter 6 port functions user's manual u12013ej3v2ud 6.2.8 port 6 port 6 is an 8-bit i/o port with an output latch. pins p60 to p67 can be set to input or output mode in 1-bit units using port mode register 6 (pm6). this port has functions related to pull-up resistors as shown below. these functions differ depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask rom model or flash memory model is used. table 6-4. pull-up resistor of port 6 higher 4 bits (p64 to p67 pins) lower 4 bits (p60 to p63 pins) mask rom on-chip pull-up resistor can be connected in 4-bit pull-up resistor can be connected in 1-bit version units by puo6 units by mask option flash memory version pull-up resistor is not connected puo6: bit 6 of pull-up resistor option register l (puol) pins p60 to p63 can drive leds directly. alternate functions include a control signal output function in external memory expansion mode. reset input sets port 6 to input mode. figures 6-13 and 6-14 show block diagrams of port 6. cautions 1. when an external wait is not used in external memory expansion mode, p66 can be used as an i/o port. 2. the value of the low-level input leakage current flowing to the p60 to p63 pins differ depending on the following conditions: [mask rom version] when pull-up resistor is connected: always ? a (max.) when pull-up resistor is not connected for duration of 1.5 clocks (no wait) note when instruction such as mov instruction to read port 6 (p6) and port mode register 6 (pm6) is executed: ?00 a (max.) other than above: ? a (max.) [flash memory version] for duration of 1.5 clocks (no wait) note when instruction such as mov instruction to read port 6 (p6) and port mode register 6 (pm6) is executed: ?00 a (max.) other than above: ? a (max.) note at this time, on-chip pull-up resistors are enabled. 133 chapter 6 port functions user's manual u12013ej3v2ud figure 6-13. block diagram of p60 to p63 pm: port mode register rd: port 6 read signal wr: port 6 write signal figure 6-14. block diagram of p64 to p67 puo: pull-up resistor option register pm: port mode register rd: port 6 read signal wr: port 6 write signal wr pm wr port rd v dd0 selector output latch (p60 to p63) pm60 to pm63 internal bus p60 to p63 mask option resistor mask rom versions only. flash memory versions have no pull-up resistors. p-ch wr pm wr port rd wr puo v dd0 selector puo6 output latch (p64 to p67) pm64 to pm67 internal bus p64/rd, p65/wr, p66/wait, p67/astb 134 chapter 6 port functions user's manual u12013ej3v2ud 6.2.9 port 7 this is a 3-bit i/o port with an output latch. pins p70 to p72 can be set to input or output mode in 1-bit units using port mode register 7 (pm7). when pins p70 to p72 are used as an input port, an on-chip pull-up resistor can be connected in 3-bit units using pull-up resistor option register l (puol). alternate functions include serial interface channel 2 data i/o and clock i/o. reset input sets port 7 to input mode. figures 6-15 and 6-16 show a block diagram of port 7. caution when used as serial interface pins, set input/output and the output latch according to the function. for the setting method, see table 19-2 serial interface channel 2 operating mode setting. figure 6-15. block diagram of p70 puo: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo7 output latch (p70) pm70 internal bus p70/si2/rxd0 135 chapter 6 port functions user's manual u12013ej3v2ud figure 6-16. block diagram of p71 and p72 puo: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo7 output latch (p71 and p72) pm71, pm72 internal bus alternate function p71/so2/txd0, p72/sck2/asck 136 chapter 6 port functions user's manual u12013ej3v2ud 6.2.10 port 12 this is an 8-bit i/o port with an output latch. pins p120 to p127 can be set to input or output mode in 1-bit units using port mode register 12 (pm12). when pins p120 to p127 are used as an input port, an on-chip pull-up resistor can be connected in 8-bit units using pull-up resistor option register h (puoh). these pins have an alternate function, serving as real-time outputs. reset input sets port 12 to input mode. figure 6-17 shows a block diagram of port 12. figure 6-17. block diagram of p120 to p127 puo: pull-up resistor option register pm: port mode register rd: port 12 read signal wr: port 12 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo12 output latch (p120 to p127) pm120 to pm127 internal bus p120/rtp0 to p127/rtp7 137 chapter 6 port functions user's manual u12013ej3v2ud 6.2.11 port 13 this is a 2-bit i/o port with an output latch. pins p130 and p131 can be set to input mode/output mode in 1-bit units using port mode register 13 (pm13). when pins p130 and p131 are used as an input port, an on-chip pull-up resistor can be connected in 2-bits using pull-up resistor option register h (puoh). these pins have an alternate function, serving as d/a converter analog outputs. reset input sets port 13 to input mode. figure 6-18 shows a block diagram of port 13. caution when only one of the d/a converter channels is used with av ref1 < v dd0 , the other pins that are not used as analog outputs must be set as follows: set the pm13 bit of port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss0 . clear the pm13x bit of port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. figure 6-18. block diagram of p130 and p131 puo: pull-up resistor option register pm: port mode register rd: port 13 read signal wr: port 13 write signal p-ch wr pm wr port rd wr puo v dd0 selector puo13 output latch (p130 and p131) pm130, pm131 internal bus p130/ano0, p131/ano1 138 chapter 6 port functions user's manual u12013ej3v2ud 6.3 port function control registers the following four types of registers control the ports. port mode registers (pm0 to pm3, pm5 to pm7, pm12, pm13) pull-up resistor option registers (puoh, puol) memory expansion mode register (mm) key return mode register (krm) (1) port mode registers (pm0 to pm3, pm5 to pm7, pm12, pm13) these registers are used to set port input/output in 1-bit units. pm0 to pm3, pm5 to pm7, pm12, and pm13 are independently set with a 1-bit or 8-bit memory manipulation instruction reset input sets these registers to ffh. when port pins are used as the alternate-function pins, set the port mode register and output latch according to table 6-5. cautions 1. pins p00 and p07 are input-only pins. 2. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. the memory expansion mode register (mm) specifies the input/output mode of pins p40 to p47. 139 chapter 6 port functions user's manual u12013ej3v2ud table 6-5. port mode register and output latch settings when using alternate functions p00 intp0 input 1 (fixed) none ti00 input 1 (fixed) none p01 intp1 input 1 ti01 input 1 p02 to p05 intp2 to intp5 input 1 p07 note 1 xt1 input 1 (fixed) none p10 to p17 note 1 ani0 to ani7 input 1 p30 to p32 to0 to to2 output 0 0 p33, p34 ti1, ti2 input 1 p35 pcl output 0 0 p36 buz output 0 0 p40 to p47 ad0 to ad7 i/o note 2 p50 to p57 a8 to a15 output note 2 p64 rd output note 2 p65 wr output note 2 p66 wait input note 2 p67 astb output note 2 p120 to p127 rtp0 to rtp7 output 0 desired value p130, p131 note 1 ano0, ano1 output 1 alternate function name p pm i/o pin name notes 1. if these ports are read out when these pins are used in the alternate-function mode, undefined values are read. 2. when the p40 to p47 pins, p50 to p57 pins, and p64 to p67 pins are used for alternate functions, set the function by the memory extension mode register (mm). cautions 1. when not using an external wait in the external memory extension mode, the p66 pin can be used as an i/o port. 2. when port 2 and port 7 are used for the serial interface, input/output and the output latch must be set according to the function. for the setting methods, see figure 16-4 format of serial operation mode register 0, figure 17-4 format of serial operation mode register 0, figure 18-3 format of serial operation mode register 1, and table 19-2 serial interface channel 2 operating mode settings. remark : don t care pm : port mode register p : port output latch 140 chapter 6 port functions user's manual u12013ej3v2ud figure 6-19. port mode register format pm0 pm1 pm2 1 1 pm03 pm02 pm01 1 76543210 symbol pm3 pm5 ff20h ff21h ff22h ff23h ff25h ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w address after reset r/w pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm6 pm7 ff26h ff27h ffh ffh r/w r/w pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 1 1 1 1 1 pm72 pm71 pm70 pm05 pm04 pm12 pm13 pmmn pmn pin i/o mode selection (m = 0 to 3, 5 to 7, 12, 13 : n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff2ch ff2dh ffh ffh r/w r/w pm122 pm121 pm120 111111 pm131 pm130 pm125 pm124 pm123 pm127 pm126 141 chapter 6 port functions user's manual u12013ej3v2ud (2) pull-up resistor option registers (puoh, puol) these registers are used to set whether to use an on-chip pull-up resistor at each port or not. a pull-up resistor is internally used at bits set to the input mode in a port where on-chip pull-up resistor use has been specified with puoh, puol. no on-chip pull-up resistors can be used for bits set to the output mode or bits used as an analog input pin, irrespective of the puoh or puol setting. puoh and puol are set with a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. cautions 1. pins p00 and p07 do not incorporate a pull-up resistor. 2. when ports 1, 4, 5, and pins p64 to p67 are used as alternate-function pins, an on-chip pull-up resistor cannot be used even if the puom bit of puoh, puol (m = 1, 4 to 6) is set to 1. 3. pins p60 to p63 can be connected to pull-up resistors by a mask option only for mask rom versions. figure 6-20. format of pull-up resistor option register caution be sure to clear bits 0 to 3, 6, and 7 of puoh to 0. puo7 puo6 puo5 puo4 puo2 puo1 puo0 puol puom pm internal pull-up resistor selection (m = 0 to 7, 12, 13) 0 1 internal pull-up resistor not used internal pull-up resistor used fff7h 00h r/w <7> <6> <5> <4> puo3 <3> <2> <0> <1> 00 puo13 puo12 0 00 puoh fff3h 00h r/w 7 6 <5> <4> symbol address after reset r/w 0 76 3 2 0 1 142 chapter 6 port functions user's manual u12013ej3v2ud (3) memory expansion mode register (mm) this register is used to set the input/output mode of port 4. mm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 6-21. format of memory expansion mode register note the full address mode allows external expansion for all areas of the 64 kb address space, except the internal rom, ram, sfr, and use-prohibited areas. remarks 1. pins p60 to p63 enter the port mode in both the single-chip and memory expansion mode. 2. besides setting port 4 input/output mode, mm also sets the wait count and external expansion area. 0 0 pw1 0 mm fff8h 10h r/w 76 5432 symbol address after reset r/w 1 pw0 mm2 mm1 mm0 0 mm2 mm1 mm0 000 001 011 100 101 111 other than above setting prohibited single-chip/memory expansion mode selection single-chip mode 256-byte mode 4 kb mode 16 kb mode full note address mode memory expansion mode ad0 to ad7 input out- put port mode p40 to p47 p40 to p47, p50 to p57, p64 to p67 pin state pw1 pw0 0 0 0 1 1 1 0 1 wait control no wait wait (one wait state inserted) setting prohibited wait control by external wait pin p56, p57 p64 to p67 port mode port mode port mode port mode a14, a15 a12, a13 p64 = rd p65 = wr p66 = wait p67 = astb p50 to p53 p54, p55 a8 to a11 143 chapter 6 port functions user's manual u12013ej3v2ud (4) key return mode register (krm) this register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 6-22. format of key return mode register caution when falling edge detection of port 4 is used, krif should be cleared to 0 (it is not cleared to 0 automatically). krif key return signal detection flag 0 1 not detected detected (falling edge detection of port 4) 000 0 krm fff6h 76 5432 symbol <1> 0 krmk krif <0> 0 krmk standby mode control by key return signal 0 1 standby mode release enabled standby mode release disabled address after reset r/w 02h r/w 144 chapter 6 port functions user's manual u12013ej3v2ud 6.4 port operations port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 6.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 145 chapter 6 port functions user's manual u12013ej3v2ud 6.5 selection of mask option the following mask option is provided in mask rom versions. the flash memory versions have no mask options. table 6-6. comparison between mask rom version and flash memory version pin name mask rom version flash memory version mask option for pins p60 to p63 on-chip pull-up resistors can be selected in 1-bit units. no on-chip pull-up resistor 146 user's manual u12013ej3v2ud chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 1 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates at a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, not using the internal feedback resistor can be set by the processor clock control register (pcc). this enables a decrease in the power consumption in stop mode. 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration control registers processor clock control register (pcc) oscillation mode select register (osms) oscillator main system clock oscillator subsystem clock oscillator 147 chapter 7 clock generator user's manual u12013ej3v2ud figure 7-1. clock generator block diagram subsystem clock oscillator main system clock oscillator x2 x1 xt2 xt1/p07 frc stop mcc frc cls css pcc2 pcc1 internal bus standby controller to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx prescaler clock to peripheral hardware prescaler oscillation mode select register watch timer, clock output function f xx cpu clock (f cpu ) wait controller scaler selector f x f xt 2 f x mcs processor clock control register 2 f xt pcc0 3 selector 1/2 148 chapter 7 clock generator user's manual u12013ej3v2ud 7.3 clock generator control registers the clock generator is controlled by the following two registers. processor clock control register (pcc) oscillation mode select register (osms) (1) processor clock control register (pcc) pcc sets the cpu clock selection, division ratio, main system clock oscillator operation/stop and whether to use the subsystem clock oscillator internal feedback resistor note . pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc to 04h. note the feedback resistor is necessary for adjusting the bias point of an oscillated waveform to the middle level of the supply voltage. only when the subsystem clock is not used, the current consumption in the stop mode can be further reduced by setting bit 6 (frc) of pcc to 1. figure 7-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2 149 chapter 7 clock generator user's manual u12013ej3v2ud figure 7-3. format of processor clock control register notes 1. bit 5 is a read-only bit. 2. this bit can be set to 1 only when the subsystem clock is not used. 3. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. caution be sure to clear bit 3 to 0. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. mcs: bit 0 of oscillation mode select register (osms) mcc frc cls css pcc2 pcc1 pcc0 pcc cls 0 1 main system clock subsystem clock fffbh 04h r/w note 1 <7> <6> <5> <4> symbol address after reset r/w 0 32 0 1 css 0 0f xx /2 pcc2 cpu ciock selection (f cpu ) pcc1 pcc0 cpu clock status 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 f xx /2 2 f xx /2 3 f xx /2 4 f xt /2 f xx setting prohibited other than above frc 0 1 internal feedback resistor used internal feedback resistor not used note 2 subsystem clock feedback resistor selection mcc 0 1 oscillation possible oscillation stopped main system clock oscillation control note 3 r/w r/w r/w r f x /2 f x /2 2 f x /2 3 f x /2 4 f x f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 mcs = 1 mcs = 0 0 1 150 chapter 7 clock generator user's manual u12013ej3v2ud the fastest instruction of the pd780058, 780058y subseries is executed in 2 cpu clocks. therefore, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in table 7- 2. table 7-2. relationship between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x 0.4 s f x /2 0.8 s f x /2 2 1.6 s f x /2 3 3.2 s f x /2 4 6.4 s f x /2 5 12.8 s f xt /2 122 s f x = 5.0 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 151 chapter 7 clock generator user's manual u12013ej3v2ud cautions 1. writing to osms should be performed only immediately after reset signal release and before peripheral hardware operation starts. as shown in figure 7-5 below, writing data (including the same data as previously) to osms causes a main system clock cycle delay of up to 2/ f x during the write operation. therefore, if this register is written during the operation, in peripheral hardware which operates on the main system clock, a temporary error occurs in the count clock cycle of timer, etc. in addition, because the oscillation mode is changed by this register, the clock for peripheral hardware as well as that for the cpu is switched. figure 7-5. main system clock waveform due to writing to osms 2. when writing 1 to mcs, v dd must be 2.7 v or higher before the write operation. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency (2) oscillation mode select register (osms) this register specifies whether the clock output from the main system clock oscillator without passing through the divider is used as the main system clock, or the clock output via the divider is used as the main system clock. osms is set with an 8-bit memory manipulation instruction. reset input clears osms to 00h. figure 7-4. format of oscillation mode selection register write to osms (mcs 0) f xx max. 2/f x operating at f xx = f x /2 (mcs = 0) operating at f xx = f x /2 (mcs = 0) mcs main system clock divider control 0 1 divider used divider not used 000 0 osms fff2h 76 5432 symbol 1 0 mcs 0 0 address after reset r/w 00h w 0 152 chapter 7 clock generator user's manual u12013ej3v2ud 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and the inverse signal to the x2 pin. figure 7-6 shows an external circuit of the main system clock oscillator. figure 7-6. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock cautions 1. do not execute the stop instruction or set mcc (bit 7 of the processor clock control register (pcc)) to 1 if an external clock is used. otherwise, the operation of the main system clock will be stopped and the x2 pin will be pulled up to vdd1. 2. when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in figures 7-6 and 7-7 to prevent any effects from wiring capacities. minimize the wiring length. do not allow wiring to intersect with other signal conductors. do not allow wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss1 . do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. crystal or ceramic resonator ic x1 x2 x1 x2 external clock v ss1 153 chapter 7 clock generator user's manual u12013ej3v2ud 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the xt1 pin and an antiphase clock signal to the xt2 pin. figure 7-7 shows an external circuit of the subsystem clock oscillator. figure 7-7. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock caution when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in figures 7-6 and 7-7 to prevent any effects from wiring capacities. minimize the wiring length. do not allow wiring to intersect with other signal conductors. do not allow wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of vss1. do not ground to any ground pattern where high current is present. do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption. external clock xt2 xt1 pd74hcu04 xt2 xt1 32.768 khz ic v ss1 154 chapter 7 clock generator user's manual u12013ej3v2ud 7.4.3 example of resonator with bad connection figure 7-8 shows examples of resonators with bad connections. figure 7-8. examples of resonator with bad connection (1/2) (a) too long wiring (b) crossed signal lines x1 high current ic x2 v ss1 ic ac pnm x1 high current x2 v dd b v ss1 x1 ic x2 v ss1 x1 portn (n = 0 to 7, 12, 13) v ss1 ic x2 (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. 155 chapter 7 clock generator user's manual u12013ej3v2ud figure 7-8. examples of resonator with bad connection (2/2) (e) signals are fetched ic x1 x2 v ss1 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution if xt2 and xt1 are wired in parallel, the cross-talk noise of x1 may increase with xt2, resulting in malfunction. to prevent this, it is recommended to wire xt2 and x1 so that they are not in parallel, and to connect the ic pin between xt2 and x1 directly to v ss1 . 7.4.4 divider the divider divides the main system clock oscillator output (f xx ) and generates various clocks. 7.4.5 when not using subsystem clock if it is not necessary to use the subsystem clock for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1: connect to v dd0 xt2: leave open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to suppress the leakage current, disconnect the above internal feedback resistor by setting bit 6 (frc) of the processor clock control register (pcc) to 1. in this case also, connect the xt1 and xt2 pins as described above. 156 chapter 7 clock generator user's manual u12013ej3v2ud 7.5 clock generator operations the clock generator generates the following clocks and controls the cpu operating mode including the standby mode. main system clock f xx subsystem clock f xt cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined by the processor clock control register (pcc) and the oscillation mode selection register (osms). (a) upon generation of the reset signal, the lowest speed mode of the main system clock (12.8 s when operated at 5.0 mhz) is selected (pcc = 04h, osms = 00h). main system clock oscillation stops while a low level is applied to the reset pin. (b) with the main system clock selected, one of the six types of minimum instruction execution times (0.4 s, 0.8 s, 1.6 s, 3.2 s, 6.4 s, 12.8 s @ 5.0 mhz) can be selected by setting the pcc and osms registers. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. in a system where the subsystem clock is not used, the current consumption in the stop mode can be further reduced by specifying with not to use the feedback resistor using bit 6 (frc) of the pcc register. (d) the pcc register can be used to select the subsystem clock and to operate the system on a low current consumption (122 s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped by the pcc register. the halt mode can be used, but not the stop mode. (subsystem clock oscillation cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the 16-bit timer/event counter, watch timer, and clock output functions only. thus, the 16-bit timer/event counter (when selecting watch timer output as the count clock when operating on the subsystem clock), the watch function, and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate on the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation). 157 chapter 7 clock generator user's manual u12013ej3v2ud 7.5.1 main system clock operations when operating on the main system clock (with bit 5 (cls) of the processor clock control register (pcc) cleared to 0), the following operations are carried out by pcc settings. (a) because the operation guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc register. (b) if bit 7 (mcc) of the pcc register is set to 1 when operating on the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of pcc is set to 1 and the operation is subsequently switched to the subsystem clock (cls = 1), the main system clock oscillation stops (see figure 7-9 ). figure 7-9. main system clock stop function (1/2) (a) operation when mcc is set after setting css in case of main system clock operation (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop. 158 chapter 7 clock generator user's manual u12013ej3v2ud figure 7-9. main system clock stop function (2/2) (c) operation when css is set after setting mcc in case of main system clock operation 7.5.2 subsystem clock operations when operating on the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 s when operating at 32.768 khz) irrespective of bits 0 to 2 (pcc0 to pcc2) of the pcc register. (b) the watchdog timer stops counting. caution do not execute the stop instruction while the subsystem clock is in operation. mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 159 chapter 7 clock generator user's manual u12013ej3v2ud 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc; operation continues on the pre- switchover clock for several instructions (see table 7-3 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed using bit 5 (cls) of the pcc register. 160 chapter 7 clock generator user's manual u12013ej3v2ud table 7-3. maximum time required for cpu clock switchover 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 css 0 0 0 0 pcc0 pcc1 pcc2 1 1 pcc0 css pcc2 pcc1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 1 8 instructions 2 instructions 4 instructions 4 instructions 16 instructions 2 instructions 8 instructions 4 instructions 4 instructions 2 instructions 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 2 instructions f x /2f xt instruction (77 instructions) f x /4f xt instruction (39 instructions) f x /8f xt instruction (20 instructions) f x /32f xt instruction (5 instructions) f x /16f xt instruction (10 instructions) f x /4f xt instruction (39 instructions) f x /8f xt instruction (20 instructions) f x /32f xt instruction (5 instructions) f x /16f xt instruction (10 instructions) f x /64f xt instruction (3 instructions) mcs = 1 mcs = 0 set values after switchover set values before switchover css css css css css 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction css 1 instruction 1 instruction remarks 1. one instruction is executed in the minimum instruction execution time with the pre-switchover cpu clock. 2. mcs: bit 0 of the oscillation mode selection register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. caution selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switchover from the main system clock to the subsyst em clock (changing css from 0 to 1) should not be performed simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). pcc0 pcc1 pcc2 pcc1 pcc2 pcc0 pcc1 pcc2 pcc0 pcc1 pcc2 pcc0 pcc1 pcc2 pcc0 pcc1 pcc2 pcc0 161 chapter 7 clock generator user's manual u12013ej3v2ud 7.6.2 system clock and cpu clock switching procedure this section describes the procedure for switching between the system clock and the cpu clock. figure 7-10. switching between system clock and cpu clock (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, the main system clock starts oscillation. at this time, the oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (12.8 s when operated at 5.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the processor clock control register (pcc) and oscillation mode selection register (osms) are rewritten and the maximum-speed operation is carried out. (3) upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) upon detection of v dd voltage reset due to an interrupt request signal, bit 7 (mcc) of pcc is cleared to 0 and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc and osms registers are rewritten and the maximum-speed operation is resumed. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. v dd reset interrupt request signal system clock cpu clock wait (26.2 ms: 5.0 mhz) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f xx f xx f xt f xx high-speed operation 162 user's manual u12013ej3v2ud chapter 8 16-bit timer/event counter 8.1 16-bit timer/event counter functions the 16-bit timer/event counter (tm0) has the following functions. interval timer pwm output pulse width measurement external event counter square-wave output one-shot pulse output pwm output and pulse width measurement can be used at the same time. (1) interval timer tm0 generates interrupt requests at the preset time interval. table 8-1. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle ? 1/f x ? 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 s) (3.2 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz (2) pwm output tm0 can generate 14-bit resolution pwm output. (3) pulse width measurement tm0 can measure the pulse width of an externally input signal. (4) external event counter tm0 can measure the number of pulses of an externally input signal. 163 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (5) square-wave output tm0 can output a square wave with any selected frequency. table 8-2. 16-bit timer/event counter square-wave output ranges minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle ? 1/f x ? 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 s) (3.2 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz (6) one-shot pulse output tm0 is able to output a one-shot pulse with any output pulse width. 164 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.2 16-bit timer/event counter configuration the 16-bit timer/event counter consists of the following hardware. table 8-3. 16-bit timer/event counter configuration item configuration timer register 16 bits 1 (tm0) register capture/compare register: 16 bits 2 (cr00, cr01) timer outputs 1 (to0) control registers timer clock select register 0 (tcl0) 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register (toc0) port mode register 3 (pm3) external interrupt mode register 0 (intm0) sampling clock select register (scs) note note see figure 21-1 basic configuration of interrupt function . 165 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-1. block diagram of 16-bit timer/event counter notes 1. edge detector 2. the configuration of the 16-bit timer/event counter output controller is shown in figure 8-2. tcl06 tcl05 tcl04 timer clock select register 0 3 internal bus capture/compare control register 0 crc02 crc01 crc00 selector ti01/ p01/intp1 inttm3 2f xx f xx f xx /2 f xx /2 2 selector 16-bit capture/compare control register (cr01) internal bus 16-bit capture/compare control register (cr00) clear match clear circuit tmc03 tmc02 tmc01 ovf0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 16-bit timer mode control register 16-bit timer output control register 2 pwm pulse output controller 16-bit timer/event counter output controller note 2 tmc01 to tmc03 intp0 inttm01 to0/p30 intp1 inttm00 match tmc01 to tmc03 3 16-bit timer register (tm0) ti00/p00/ intp0 note 1 crc02 166 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-2. block diagram of 16-bit timer/event counter output controller remark the circuitry enclosed by the broken line is the output controller. pwm pulse output controller edge detector ti00/p00/ intp0 ospt 16-bit timer output control register ospe toc04 lvs0 lvr0 toc01 toe0 selector selector inv s r q 3 level inversion crc02 inttm01 crc00 inttm00 one-shot pulse output controller 2 es11 es10 external interrupt mode register 0 16-bit timer mode control register tmc03 tmc02 tmc01 p30 output latch pm30 port mode register 3 to0/p30 internal bus 167 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (1) capture/compare register 00 (cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0. (a) when cr00 is used as a compare register the value set in cr00 is constantly compared with the 16-bit timer register (tm0) count value, and an interrupt request (inttm00) is generated if they match. it can also be used as the register that holds the interval time when tm0 is set to interval timer operation, and as the register that sets the pulse width when tm0 is set to pwm output operation. (b) when cr00 is used as a capture register it is possible to select the valid edge of the intp0/ti00 pin or the intp1/ti01 pin as the capture trigger. the intp0/ti00 or intp1/ti01 valid edge is set by external interrupt mode register 0 (intm0). if cr00 is specified as a capture register and the capture trigger is specified to be the valid edge of the intp0/ti00 pin, the situation is as shown in table 8-4. on the other hand, when the capture trigger is specified to be the valid edge of the intp1/ti01 pin, the situation is as shown in table 8-5. table 8-4. intp0/ti00 pin valid edge and cr00 capture trigger valid edge es11 es10 intp0/ti00 pin valid edge cr00 capture trigger valid edge 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited 1 1 both rising and falling edges no capture operation table 8-5. intp1/ti01 pin valid edge and cr00 capture trigger valid edge es21 es20 intp1/ti01 pin valid edge cr00 capture trigger valid edge 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited 1 1 both rising and falling edges both rising and falling edges cr00 is set with a 16-bit memory manipulation instruction. reset input makes cr00 undefined. cautions 1. set the data of pwm (14 bits) to the higher 14 bits of cr00. at this time, clear the lower 2 bits to 00. 2. set cr00 to a value other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr00 is set to 0000h, an interrupt request (inttm00) is generated following overflow (ffffh). 3. if the new value of cr00 is less than the value of the 16-bit timer register (tm0), tm0 continues counting, overflows, and then starts counting again from 0. if the new value of cr00 is less than the old value, the timer must be restarted after changing the value of cr00. 168 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (2) capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0. (a) when cr01 is used as a compare register the value set in cr01 is constantly compared with the 16-bit timer register (tm0) count value, and an interrupt request (inttm01) is generated if they match. (b) when cr01 is used as a capture register it is possible to select the valid edge of the intp0/ti00 pin as the capture trigger. the intp0/ti00 valid edge is set by external interrupt mode register 0 (intm0). table 8-6. intp0/ti00 pin valid edge and cr01 capture trigger valid edge es11 es10 intp0/ti00 pin valid edge cr01 capture trigger valid edge 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited 1 1 both rising and falling edges both rising and falling edges cr01 is set with a 16-bit memory manipulation instruction. reset input makes cr01 undefined. caution set cr01 to a value other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr01 is set to 0000h, an interrupt request (inttm01) is generated following overflow (ffffh). (3) 16-bit timer register (tm0) tm0 is a 16-bit register which counts the count pulses. tm0 is read with a 16-bit memory manipulation instruction. when tm0 is read, the capture/compare register (cr01) should first be set as a capture register. reset input clears tm0 to 0000h. caution as reading of the value of tm0 is performed via cr01, the previously set value of cr01 is lost. 169 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.3 16-bit timer/event counter control registers the following seven registers are used to control the 16-bit timer/event counter. timer clock select register 0 (tcl0) 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register (toc0) port mode register 3 (pm3) external interrupt mode register 0 (intm0) sampling clock select register (scs) (1) timer clock select register 0 (tcl0) this register is used to set the count clock of the 16-bit timer register. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tcl0 to 00h. remark tcl0 has the function of setting the pcl output clock in addition to that of setting the count clock of the 16-bit timer register. 170 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-3. format of timer clock select register 0 cautions 1. the ti00/intp0 pin valid edge is set by external interrupt mode register 0 (intm0), and the sampling clock frequency is selected by the sampling clock selection register (scs). 2. when enabling pcl output, set tcl00 to tcl03, then set cloe to 1 with a 1-bit memory manipulation instruction. 3. to read the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from 16-bit capture/compare register 01 (cr01). 4. when rewriting tcl0 to other data, stop the timer operation beforehand. cloe tcl06 tcl05 tcl04 tcl03 tcl02 tcl01 tcl00 <7> 6 5 4 3 2 1 0 symbol tcl0 tcl03 tcl02 tcl01 tcl00 0000f xt (32.768 khz) 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 1 pcl output clock selection mcs = 0 ff40h 00h r/w address after reset r/w other than above setting prohibited tcl06 tcl05 tcl04 0 0 0 ti00 (valid edge specifiable) 0012f xx setting prohibited f x (5.0 mhz) 010f xx f x (5.0 mhz) f x /2 (2.5 mhz) 011f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 100f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1 1 1 watch timer output (inttm 3) mcs = 1 16-bit timer register count clock selection mcs = 0 other than above setting prohibited cloe 1 output enabled pcl output control 0 output disabled 171 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00: 16-bit timer/event counter input pin 5. tm0: 16-bit timer register 6. mcs: bit 0 of oscillation mode select register (osms) 7. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. (2) 16-bit timer mode control register (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0 to 00h. caution the 16-bit timer register starts operation at the moment tmc01 to tmc03 are set to values other than 0, 0, 0 (operation stop mode). set tmc01 to tmc03 to 0, 0, 0 to stop the operation. 172 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-4. format of 16-bit timer mode control register cautions 1. switch the clear mode and the to0 output timing after stopping the timer operation (by clearing tmc01 to tmc03 to 0, 0, 0). 2. set the valid edge of the ti00/intp0 pin using external interrupt mode register 0 (intm0) and select the sampling clock frequency using the sampling clock select register (scs). 3. when using the pwm mode, set the pwm mode and then set data to cr00. 4. if clear & start mode entered on a match between tm0 and cr00 is selected, when the set value of cr00 is ffffh and the tm0 value changes from ffffh to 0000h, the ovf0 flag is set to 1. remark to0: 16-bit timer/event counter output pin ti00: 16-bit timer/event counter input pin tm0: 16-bit timer register cr00: compare register 00 cr01: compare register 01 0000 tmc03 tmc02 tmc01 ovf0 7654321<0> symbol tmc0 ff48h 00h r/w address after reset r/w ovf0 16-bit timer register overflow detection 0 overflow not detected 1 overflow detected tmc03 tmc02 tmc01 operating mode or clear mode selection to0 output timing selection interrupt request generation 000 operation stopped (tm0 cleared to 0) no change not generated 001 pwm mode (free running) pwm pulse output 010 011 100 101 110 111 free-running mode match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge clear & start on ti00 valid edge clear & start on match between tm0 and cr00 generated on match between tm0 and cr00, and match between tm0 and cr01 173 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (3) capture/compare control register 0 (crc0) this register controls the operation of capture/compare registers 00 and 01 (cr00 and cr01). crc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 to 04h. figure 8-5. format of capture/compare control register 0 cautions 1. timer operation must be stopped before setting crc0. 2. when clear & start mode entered on a match between tm0 and cr00 is selected by the 16-bit timer mode control register (tmc0), cr00 should not be specified as a capture register. 0000 0 crc02 crc01 crc00 76543210 symbol crc0 ff4ch 04h r/w address after reset r/w crc00 cr00 operating mode selection 0 operates as compare register 1 operates as capture register crc01 cr00 capture trigger selection captures on valid edge of ti01 captures on reverse phase of valid edge of ti00 0 1 crc02 cr01 operating mode selection operates as compare register operates as capture register 0 1 174 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (4) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter output controller. it sets r-s type flip- flop (lv0) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and the output trigger for a one-shot pulse by software. toc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0 to 00h. 175 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-6. format of 16-bit timer output control register cautions 1. timer operation must be stopped before setting toc0 (except ospt). 2. if lvs0 and lvr0 are read after data is set, they will be 0. 3. ospt is cleared automatically after data setting, and will therefore be 0 if read. 4. ospt can be set only when ospe = 1. 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 7 <6> <5> 4 <3> <2> 1 <0> symbol toc0 ff4eh 00h r/w address after reset r/w toe0 16-bit timer/event counter output control 0 output disabled (port mode) 1 output enabled toc01 0 1 in pwm mode in other modes active level selection timer output f/f control by match of cr00 and tm0 active high active low inversion operation disabled inversion operation enabled lvs0 lvr0 16-bit timer/event counter timer output f/f status setting 00 no change 01 timer output f/f reset to 0 10 timer output f/f set to 1 11 setting prohibited toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled ospe one-shot pulse output control 0 continuous pulse output 1 one-shot pulse output ospt control of one-shot pulse output trigger by software 0 one-shot pulse trigger not used 1 one-shot pulse trigger used 176 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p30/to0 pin for timer output, set pm30 and the output latch of p30 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 8-7. format of port mode register 3 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 symbol pm3 ff23h ffh r/w address after reset r/w pm3n p3n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 177 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (6) external interrupt mode register 0 (intm0) this register is used to set the valid edges of intp0 to intp2, ti00, and ti01. intm0 is set with an 8-bit memory manipulation instruction. reset input clears intm0 to 00h. figure 8-8. format of external interrupt mode register 0 caution when using the intp0/ti00/p00 and intp1/ti01/p01 pins as timer input pins (ti00 and ti01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (tmc01 to tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0, 0, before setting the valid edge of ti00 and ti01. when using the intp0/ti00/p00 and intp1/ti01/p01 pins as external interrupt input pins (intp0 and intp1), the valid edge of intp0 and intp1 may be set while 16-bit timer 0 is operating. es31 es30 es21 es20 es11 es10 0 0 76543210 symbol intm0 ffech 00h r/w address after reset r/w es11 intp0/ti00 valid edge selection es10 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both rising and falling edges 1 es21 intp1/ti01 valid edge selection es20 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both rising and falling edges 1 es31 intp2 valid edge selection es30 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both rising and falling edges 1 178 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (7) sampling clock select registers (scs) this register sets the clock used as the clock for sampling the valid edges input to intp0. when remote controlled reception is carried out using intp0, digital noise is eliminated by the sampling clock. scs is set with an 8-bit memory manipulation instruction. reset input clears scs to 00h. figure 8-9. format of sampling clock select register caution f xx /2 n is the clock supplied to the cpu, and f xx /2 5 , f xx /2 6 , and f xx /2 7 are clocks supplied to peripheral hardware. the f xx /2 n clock is stopped in halt mode. remarks 1. n: value set to bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) (n = 0 to 4) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs: bit 0 of oscillation mode select register (osms) 5. values in parentheses apply to operation with f x = 5.0 mhz. 0 0 0 0 0 0 scs1 scs0 76543210 symbol scs ff47h 00h r/w address after reset r/w scs1 scs0 00 01 10 11 intp0 sampling clock selection mcs = 1 mcs = 0 f xx /2 n f x /2 7 (39.1 khz) f xx /2 7 f x /2 8 (19.5 khz) f x /2 5 (156.3 khz) f xx /2 5 f x /2 6 (78.1 khz) f x /2 6 (78.1 khz) f xx /2 6 f x /2 7 (39.1 khz) 179 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4 16-bit timer/event counter operations 8.4.1 interval timer operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-10 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value set to 16-bit capture/compare register 00 (cr00) beforehand as the interval. when the count value of the 16-bit timer register (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. the count clock of the 16-bit timer/event counter can be selected using bits 4 to 6 (tcl04 to tcl06) of timer clock select register 0 (tcl0). for the operation when the value of the compare register is changed during the timer/counter operation, see 8.6 (3) operation after compare register change during timer count operation . figure 8-10. control register settings for interval timer operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. 0000110/10 tmc03 tmc02 tmc01 ovf0 tmc0 clear & start on match tm0 and cr00 0 0 0 0 0 0/1 0/1 0 crc02 crc01 crc00 crc0 cr00 is set as compare register 180 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-11. interval timer configuration diagram figure 8-12. interval timer operation timings remark interval time = (n + 1) t : n = 0001h to ffffh. 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) selector f xx /2 2 f xx /2 f xx 2f xx inttm3 ti00/p00/intp0 ovf0 clear circuit inttm00 t count clock tm0 count value cr00 inttm00 to0 interval time interval time interval time 0000 0001 n 0000 0001 n 0000 0001 n count start clear clear nn nn interrupt request acknowledge interrupt request acknowledge 181 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud table 8-7. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0002 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 0 0 1 setting 2 1/f x setting 2 16 1/f x setting 1/f x prohibited (400 ns) prohibited (13.1 ms) prohibited (200 ns) 0102 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 0112 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 1002 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 s) (3.2 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 1112 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. tcl04 to tcl06: bits 4 to 6 of timer clock select register (tcl0) 4. values in parentheses apply to operation with f x = 5.0 mhz 8.4.2 pwm output operations setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) as shown in figure 8-13 allows operation as pwm output. pulses with the duty rate determined by the value set to 16-bit capture/compare register 00 (cr00) beforehand are output from the to0/ p30 pin. set the active level width of the pwm pulse to the higher 14 bits of cr00. select the active level using bit 1 (toc01) of the 16-bit timer output control register (toc0). this pwm pulse has a 14-bit resolution. the pulse can be converted to an analog voltage by integrating it with an external low-pass filter (lpf). the pwm pulse is formed by a combination of the basic cycle determined by 2 8 / and the sub-cycle determined by 2 14 / so that the time constant of the external lpf can be shortened. the count clock can be selected using bits 4 to 6 (tcl04 to tcl06) of timer clock select register 0 (tcl0). pwm output enable/disable can be selected using bit 0 (toe0) of toc0. cautions 1. pwm operation mode should be selected before setting cr00. 2. be sure to clear bits 0 and 1 of cr00 to 0. 3. do not select pwm operation mode for external clock input from the ti00/p00/intp0 pin. tcl06 tcl05 tcl04 182 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-13. control register settings for pwm output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pwm output. see the description of the respective control registers for details. : don? care tmc0 0 1 0 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 pwm mode crc00 crc01 crc02 crc0 0 0/1 0/1 0 0 0 0 0 cr00 is set as compare register toe0 toc01 lvr0 lvs0 toc04 ospe ospt toc0 1 0/1 0 to0 output enabled specifies active level 183 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud by integrating 14-bit resolution pwm pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and d/a converter applications, etc. the analog output voltage (v an ) used for d/a conversion with the configuration shown in figure 8-14 is as follows. v an = v ref 2 16 v ref : external switching circuit reference voltage figure 8-14. example of d/a converter configuration with pwm output capture/compare register 00 (cr00) value figure 8-15 shows an example in which pwm output is converted to an analog voltage and used in a voltage synthesizer type tv tuner. figure 8-15. tv tuner application circuit example switching circuit to0/p30 pwm signal v ref low-pass filter analog output (v an ) pd780058, 780058y pd780058, 780058y to0/p30 v ss0 8.2 k ? 8.2 k ? 100 pf 22 k ? +110 v 2sc 2352 47 k ? 47 k ? 47 k ? 0.22 f 0.22 f 0.22 f electronic tuner gnd pc574j v ss0 184 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4.3 ppg output operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-16 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0/p30 pin with the pulse width and the cycle that correspond to the count values set beforehand to 16-bit capture/compare register 01 (cr01) and 16-bit capture/ compare register 00 (cr00), respectively. figure 8-16. control register settings for ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark : don t care cautions 1. cr00 and cr01 should be set to values in the following range: 0000h cr01 < cr00n ffffh 2. the cycle of the pulse generated through ppg output (cr00 setting value + 1) has a duty of (cr01 setting value + 1)/(cr00 setting value + 1). tmc0 0 0 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 crc0 0 0 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register cr01 is set as compare register toc0 1 1 0/1 0/1 1 0 0 0 toe0 toc01 lvr0 lvs0 inversion of output on match of tm0 and cr00 toc04 ospe ospt to0 output enabled specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output disabled 185 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-17. configuration of ppg output figure 8-18. ppg output operation timing 16-bit timer capture/compare register 00 (cr00) 16-bit timer counter 0 (tm0) clear circuit noise eliminator f xx f xx /2 f xx /2 2 ti00/p00/intp0 16-bit timer capture/compare register 01 (cr01) to0/p30 selector output controller inttm3 2f xx t 0000h 0000h 0001h 0001h m 1 count clock tm0 count value to0 pulse width: (m + 1) t 1 cycle: (n + 1) t n cr00 capture value cr01 capture value m m n 1 n clear count start remark 0000h < m < n ffffh 186 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4.4 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/p00 pin and ti01/p01 pin using the 16-bit timer register (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00/p00 pin. (1) pulse width measurement with free-running counter and one capture register when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-17), and the edge specified by external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. any of three edge specifications can be selected rising, falling, or both edges by bits 2 and 3 (es10 and es11) of intm0. for valid edge detection, sampling is performed at the interval selected by the sampling clock select register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-19. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measure- ment. see the description of the respective control registers for details. crc0 0 0/1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register cr01 is set as capture register tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode 187 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-20. configuration diagram for pulse width measurement by free-running counter figure 8-21. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) selector f xx /2 2 f xx /2 f xx 2f xx inttm3 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) ovf0 intp0 internal bus ti00/p00/intp00 count clock tm0 count value ti00 pin input cr01 captured value intp0 ovf0 0000 0001 d0 d1 ffff 0000 d2 d3 d0 d1 d2 d3 (d1 d0) t (10000h d1 + d2) t (d3 d2) t t 188 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (2) measurement of two pulse widths with free-running counter when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00/p00 pin and the ti01/p01 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, when the edge specified by bits 4 and 5 (es20 and es21) of intm0 is input to the ti01/p01 pin, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00) and an external interrupt request signal (intp1) is set. any of three edge specifications can be selected rising, falling, or both edges as the valid edges for the ti00/p00 pin and the ti01/p01 pin by bits 2 and 3 (es10 and es11) and bits 4 and 5 (es20 and es21) of intm0, respectively. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock select register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-22. control register settings for two pulse width measurements with free-running counter (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. crc0 1 0 1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as capture register captured in cr00 on valid edge of ti01/p01 pin cr01 is set as capture register tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode 189 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-23. timing of pulse width measurement operation with free-running counter (with both edges specified) count clock tm0 count value ti00 pin input cr01 captured value intp0 ti01 pin input t cr00 captured value intp1 ovf0 (d1 d0) t (10000h d1 + d2) t (10000h d1 + (d2 + 1)) t (d3 d2) t 0000 0001 d0 d1 0000 d3 d2 ffff d0 d1 d3 d2 d1 190 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-22), it is possible to measure the pulse width of the signal input to the ti00/p00 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, on the reverse input edge to that of the capture operation into cr01, the value of tm0 is taken into 16- bit capture/compare register 00 (cr00). either of two edge specifications can be selected rising or falling as the valid edges for the ti00/p00 pin by bits 2 and 3 (es10 and es11) of intm0. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock select register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/p00 is specified to be both the rising and falling edges, capture/ compare register 00 (cr00) cannot perform the capture operation. figure 8-24. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as capture register captured in cr00 on reverse edge of valid edge of ti00/p00 pin cr01 is set as capture register 191 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-25. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) count clock tm0 count value ti00 pin input cr01 captured value cr00 captured value intp0 ovf0 (d1 d0) t (10000h d1 + d2) t (d3 d2) t d1 d3 d0 d2 d3 d2 0000 ffff d1 d0 0000 0001 t 192 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (4) pulse width measurement by means of restart when input of a valid edge to the ti00/p00 pin is detected, the count value of the 16-bit timer register (tm0) is taken into 16-bit capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00/p00 pin is measured by clearing tm0 and restarting the count (see register settings in figure 8-24). the edge specification can be selected from two types, rising and falling edges by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). in a valid edge detection, sampling is performed on the cycle selected by the sampling clock select register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/p00 is specified to be both the rising and falling edges, 16-bit capture/ compare register 00 (cr00) cannot perform the capture operation. figure 8-26. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. figure 8-27. timing of pulse width measurement operation by means of restart (with rising edge specified) tmc0 0 0/1 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on valid edge of ti00/p00 pin crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as capture register captured in cr00 on reverse edge to valid edge of ti00/p00 pin cr01 is set as capture register count clock tm0 count value ti00 pin input cr01 captured value cr00 captured value intp0 t 0000 0001 d0 0000 0001 d1 0001 0000 d2 d0 d2 d1 d1 t d2 t 193 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4.5 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00/p00 pin with the 16-bit timer register (tm0). tm0 is incremented each time the valid edge specified by external interrupt mode register 0 (intm0) is input. when the tm0 counted value matches the 16-bit capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. set cr00 to a value other than 0000h (1-pulse count operation cannot be performed). the rising edge, falling edge or both edges can be selected using bits 2 and 3 (es10 and es11) of intm0. because operations are carried out only after the valid edge is detected twice by sampling at the interval selected by the sampling clock select register (scs), noise with short pulse widths can be eliminated. figure 8-28. control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respective control registers for details. crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 194 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-29. external event counter configuration diagram figure 8-30. external event counter operation timing (with rising edge specified) caution when reading the external event counter count value, tm0 should be read. 16-bit capture/compare register 00 (cr00) clear inttm00 intp0 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) internal bus ti00 valid edge ovf0 ti00 pin input tm0 count value cr00 inttm00 n 0000 0001 0002 0003 0004 0005 n 1 n 0000 0001 0002 0003 195 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4.6 square-wave output operation the 16-bit timer/event counter outputs a square wave with any selected frequency at intervals specified by the count value set in advance to 16-bit capture/compare register 00 (cr00). the to0/p30 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of the 16-bit timer output control register (toc0) to 1. this enables a square wave with any selected frequency to be output. figure 8-31. control register settings in square-wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register toc0 1 1 0/1 0/1 0 0 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value no inversion of output on match of tm0 and cr01 one-shot pulse output disabled 196 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-32. square-wave output operation timing table 8-8. 16-bit timer/event counter square-wave output ranges minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 2 1/f x 2 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 s) (3.2 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz count clock tm0 count value cr00 inttm0 to0 pin output 0000 0001 0002 n 1 n 0000 0001 0002 n 1 n 0000 n 197 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.4.7 one-shot pulse output operation the 16-bit timer/event counter can be started in synchronization with a software trigger or external trigger (ti00/ p00 pin input) and output a one-shot pulse that ends on overflow of tm0. (1) one-shot pulse output using software trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) are set as shown in figure 8-31, and bit 6 (ospt) of toc0 is set to 1 by software, a one-shot pulse is output from the to0/p30 pin. by setting ospt to 1, the 16-bit timer/event counter is cleared and started, and output is activated by the count value (n) set beforehand to 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated note by the count value (m) set beforehand in 16-bit capture/compare register 00 (cr00). tm0 continues to operate after a one-shot pulse is output. to stop tm0, tmc0 must be set to 00h. note the case where n < m is described here. when n > m, the output becomes active with the cr00 register and inactive with the cr01 register. cautions 1. when a one-shot pulse is output by a software trigger, fix the ti00/p00 pin to either the high or low level. 2. when outputting a one-shot pulse, do not set ospt to 1. to output a one-shot pulse again, wait until the current one-shot pulse output is completed. figure 8-33. control register settings for one-shot pulse output operation using software trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details. caution do not clear cr00 and cr01 to 0000h. crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register cr01 is set as compare register toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output mode set 1 in case of output tmc0 0 0 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode 198 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-34. one-shot pulse output operation timing using software trigger caution the 16-bit timer register starts operation at the moment tmc01 to tmc03 are set to values other than 0, 0, 0 (operation stop mode). remark n < m count clock tm0 count value cr01 set value cr00 set value inttm01 ospt inttm00 to0 pin output 0000 0001 n n + 1 0000 n 1 n m 1 m m + 1 0000 n m n m n m n m set 0ch to tmc0 (tm0 count start) one-shot pulse 199 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (2) one-shot pulse output using external trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) are set as shown in figure 8-33, a one-shot pulse is output from the to0/ p30 pin with a ti00/p00 valid edge as an external trigger. any of three edge specifications can be selected rising, falling, or both edges as the valid edges for the ti00/p00 pin by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). when a valid edge is input to the ti00/p00 pin, the 16-bit timer/event counter is cleared and started, and output is activated by the count values (n) set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated note by the count value (m) set beforehand in 16-bit capture/compare register 00 (cr00). note the case where n < m is described here. when n > m, the output becomes active with the cr00 register and inactive with the cr01 register. caution when outputting one-shot pulses, the external trigger is ignored if generated again. figure 8-35. control register settings for one-shot pulse output operation using external trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details. caution do not clear cr00 and cr01 to 0000h. crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 is set as compare register cr01 is set as compare register tmc0 0 0 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on valid edge of ti00/p00 pin toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 lvs0 ospt ospe toc04 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output mode 200 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud figure 8-36. one-shot pulse output operation timing using external trigger (with rising edge specified) caution the 16-bit timer register starts operation at the moment tmc01 to tmc03 are set to values other than 0, 0, 0 (operation stop mode). remark n < m count clock tm0 count value cr01 set value cr00 set value inttm01 ti00 pin input inttm00 to0 pin output 0000 0001 0000 n n + 1 n + 2 m 2m 1 m m + 1 m + 2 m + 3 n m n m n m n m set 08h to tmc0 (tm0 count start) 201 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud 8.5 16-bit timer/event counter operating cautions (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because the 16-bit timer register (tm0) is started asynchronously to the count pulse. figure 8-37. 16-bit timer register start timing (2) 16-bit compare register setting (when in the clear & start mode entered on a match between tm0 and cr00) set 16-bit capture/compare register 00 (cr00) to the a value other than 0000h. thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot be carried out. (3) operation after compare register change during timer count operation if the value after the 16-bit capture/compare register (cr00) is changed is smaller than that of the 16-bit timer register (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value after cr00 change (m) is smaller than that before change (n), it is necessary to reset and restart the timer after changing cr00. figure 8-38. timing after change of compare register during timer count operation remark n > x > m timer start count pulse tm0 count value 0000h 0001h 0002h 0003h 0004h count pulse cr00 tm0 count value x 1 x ffffh 0000h 0001h 0002h m n 202 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (4) capture register data retention timing if the valid edge of the ti00/p00 pin is input during 16-bit capture/compare register 01 (cr01) read, cr01 holds the data without carrying out a capture operation. however, the interrupt request signal (pif0) is set upon detection of the valid edge. figure 8-39. capture register data retention timing (5) valid edge setting when using the ti00/p00/intp0 and ti01/p01/intp1 pins as timer input pins (ti00 and ti01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (tmc01 to tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0, 0, before setting the valid edge of ti00 and ti01. the valid edge is set by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). when using the ti00/p00/intp0 and ti01/p01/ intp1 pins as external interrupt input pins (intp0 and intp1), the valid edge of intp0 and intp1 may be set while 16-bit timer 0 is operating. (6) re-trigger of one-shot pulse (a) one-shot pulse output using software when outputting a one-shot pulse, do not set ospt to 1. to output a one-shot pulse again, wait until the current one-shot pulse output is completed. (b) one-shot pulse output using external trigger when outputting one-shot pulses, the external trigger is ignored if generated again. (c) one-shot pulse output function when using the software trigger for one-shot pulse output, fix the level of the ti00/p00/intp0 and ti01/ p01/intp1 pins to either the high or low level. otherwise, the external trigger will remain valid even when the software trigger is used, and the timer will be cleared and started when the level of the ti00/p00/intp0 or ti01/p01/intp1 pin changes. in consequence, the pulse will be output unexpectedly. count pulse tm0 count value edge input pif0 capture read signal cr01 captured value capture operation ignored x n + 1 n n + 1 n + 2 m m + 1 m + 2 203 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (7) operation of ovf0 flag (a) ovf0 flag setting ofv0 flag is set to 1 in the following case. when one of clear & start mode on match between tm0 and cr00, clear & start mode on ti00 valid edge, or free-running mode is selected. cr00 is set to ffffh. tm0 is counted up from ffffh to 0000h. figure 8-40. operation timing of ovf0 flag count pulse cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h (b) clear ovf0 flag even if the ovf0 flag is cleared before the next count clock is counted (before tm0 becomes 0001h) after tm0 has overflowed, the ovf0 flag is set again and the clear becomes invalid. (8) conflict operation (a) if the read period and capture trigger input conflict if the read period and inputting a capture trigger conflict while 16-bit capture/compare registers 00 and 01 (cr00 and cr01) are used as capture registers, the registers do not perform a capture operation but hold data. however, the interrupt request flag (pif0) is set when the valid edge is detected. (b) if the match timing of the write period and tm0 conflict when 16-bit capture/compare registers 00 and 01 (cr00, cr01) are used as capture registers, because match detection cannot be performed correctly if the match timing of the write period and 16-bit timer register 0 (tm0) conflict, do not write to cr00 and cr01 close to the match timing. 204 chapter 8 16-bit timer/event counter user's manual u12013ej3v2ud (9) timer operation (a) cr01 capture even if 16-bit timer register 0 (tm0) is read, a capture to 16-bit capture/compare register 01 (cr01) is not performed. (b) acknowledgement of ti00 and ti01 pins when the timer is stopped, input signals to the ti00 and ti01 pins are not acknowledged, regardless of the cpu operation. (10) capture operation (a) if the valid edge of ti00 is specified for the count clock when the valid edge of ti00 is specified for the count clock, the capture register with ti00 specified as a trigger will not operate correctly. (b) if both rising and falling edges are selected as the valid edge of ti00. when both the rising and falling edges are selected as the valid edge of ti00, cr00 cannot perform a capture operation with ti00 specified as the capture trigger. (c) to use signal from ti00 as capture trigger for an accurate capture operation, a pulse longer than twice the width of the count clock selected by the sampling clock select register (scs) is necessary. (11) compare operation (a) when rewriting cr00 and cr01 during timer operation when rewriting 16-bit timer capture/compare registers 00 and 01 (cr00, cr01), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) when cr00 and cr01 are set to compare mode when cr00 and cr01 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. (12) edge detection (a) when the ti00 or ti01 pin is high level immediately after a system reset when the ti00 or ti01 pin is high level immediately after a system reset, if the valid edge of the ti00 or ti01 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/ counter 0 (tm0) is then enabled, the rising edge will be detected immediately. care is therefore needed when the ti00 or ti01 pin is pulled up. however, when operation is enabled after being stopped, the rising or falling edge is not detected. 205 user's manual u12013ej3v2ud chapter 9 8-bit timer/event counter 9.1 8-bit timer/event counter functions for the 8-bit timer/event counter, two modes are available. one is a mode for the two 8-bit timer/event counter channels to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.1 8-bit timer/event counter mode the 8-bit timer/event counters 1 and 2 (tm1 and tm2) have the following functions. interval timer external event counter square-wave output 206 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (1) 8-bit interval timer interrupt requests are generated at the preset time intervals. table 9-1. interval times of 8-bit timer/event counters 1 and 2 minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 s) (204.8 s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (204.8 s) (409.6 s) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (409.6 s) (819.2 s) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (819.2 s) (1.64 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (1.64 ms) (3.28 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (3.28 ms) (6.55 ms) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (6.55 ms) (13.1 ms) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (13.1 ms) (26.2 ms) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (26.2 ms) (52.4 ms) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (104.9 ms) (209.7 ms) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 207 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-2. square-wave output ranges of 8-bit timer/event counters 1 and 2 minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 s) (204.8 s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (204.8 s) (409.6 s) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (409.6 s) (819.2 s) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (819.2 s) (1.64 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (1.64 ms) (3.28 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (3.28 ms) (6.55 ms) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (6.55 ms) (13.1 ms) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (13.1 ms) (26.2 ms) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (26.2 ms) (52.4 ms) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (104.9 ms) (209.7 ms) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 208 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer interrupt requests can be generated at the preset time intervals. table 9-3. interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counter minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (104.9 ms) (209.7 ms) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (209.7 ms) (419.4 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (419.4 ms) (838.9 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (838.9 ms) (1.7 s) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (1.7 s) (3.4 s) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (3.4 s) (6.7 s) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (6.7 s) (13.4 s) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (26.8 s) (53.7 s) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 209 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-4. square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counter minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (104.9 ms) (209.7 ms) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (209.7 ms) (419.4 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (419.4 ms) (838.9 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (838.9 ms) (1.7 s) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (1.7 s) (3.4 s) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (3.4 s) (6.7 s) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (6.7 s) (13.4 s) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (26.8 s) (53.7 s) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 210 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.2 8-bit timer/event counter configuration the 8-bit timer/event counter consists of the following hardware. table 9-5. 8-bit timer/event counter configuration item configuration timer register 8 bits 2 (tm1, tm2) register compare register: 8 bits 2 (cr10, cr20) timer outputs 2 (to1, to2) control registers timer clock select register 1 (tcl1) 8-bit timer mode control register 1 (tmc1) 8-bit timer output control register (toc1) port mode register 3 (pm3) note note see figure 6-9 block diagram of p30 to p37 . 211 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud figure 9-1. block diagram of 8-bit timer/event counter note see figures 9-2 and 9-3 for details of 8-bit timer/event counter output controllers 1 and 2, respectively. 8-bit compare register 10 (cr10) match 8-bit timer register 1 (tm1) selector clear selector selector f xx /2 to f xx /2 9 f xx /2 11 ti1/p33 f xx /2 to f xx /2 9 f xx /2 11 ti2/p34 4 tcl 17 tcl 16 tcl 15 tcl 14 tcl 13 tcl 12 tcl 11 tcl 10 timer clock select register 1 8-bit timer mode control register tmc12 tce2 tce1 internal bus lvs2 lvr2 toc 15 toe2 lvs1 lvr1 toc 11 toe1 4 8-bit timer register 2 (tm2) 8-bit timer/ event counter output controller 8-bit timer output control register 8-bit timer/event counter output controller 2 clear match 8-bit compare register (cr20) selector note note inttm1 to2/p32 inttm2 to1/p31 4 4 selector internal bus 212 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud figure 9-2. block diagram of 8-bit timer/event counter output controller 1 note bit 1 of port mode register 3 (pm3) remark the section in the broken lines is the output controller. figure 9-3. block diagram of 8-bit timer/event counter output controller 2 note bit 2 of port mode register 3 (pm3) remarks 1. the section in the broken lines is the output controller. 2. f sck : serial clock frequency lvr1 lvs1 toc11 inttm1 r s inv q p31 output latch toe1 pm31 note to1/p31 level f/f (lv1) lvr2 lvs2 toc15 inttm2 r s inv level f/f (lv2) f sck p32 output latch pm32 note toe2 to2/p32 q 213 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (1) compare registers 10, 20 (cr10, cr20) cr10 and cr20 are 8-bit registers used to compare the value set to cr10 to the 8-bit timer register 1 (tm1) count value, and the value set to cr20 to the 8-bit timer register 2 (tm2) count value, and, if they match, generate an interrupt request (inttm1 and inttm2, respectively). cr10 and cr20 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. when the compare register is used as 8-bit timer/event counter, between values 00h and ffh can be set. when the compare register is used as 16-bit timer/event counter, between values 0000h and ffffh can be set. reset input makes cr10 and cr20 undefined. cautions 1. before changing the set value of 8-bit compare registers 10 and 20 (cr10 and cr20) while the 16-bit timer/counter is being used, stop the operation of each of the 8-bit timer/event counters. 2. when the new values of cr10 and cr20 are less than the count values of the 8-bit timer registers (tm1 and tm2), tm1 and tm2 continue counting, overflow, and start counting again from 0. if the new values of cr10 and cr20 are less than the old values, therefore, it is necessary to restart the timers after changing the values of cr10 and cr20. (2) 8-bit timer registers 1, 2 (tm1, tm2) tm1 and tm2 are 8-bit registers used to count count pulses. when tm1 and tm2 are used in the 8-bit timer 2-channel mode, they are read with an 8-bit memory manipulation instruction. when tm1 and tm2 are used as 16-bit timer 1-channel mode, 16-bit timer register (tms) is read with a 16-bit memory manipulation instruction. reset input clears tm1 and tm2 to 00h. 214 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.3 8-bit timer/event counter control registers the following four registers are used to control the 8-bit timer/event counter. timer clock select register 1 (tcl1) 8-bit timer mode control register 1 (tmc1) 8-bit timer output control register (toc1) port mode register 3 (pm3) (1) timer clock select register 1 (tcl1) this register sets the count clock of 8-bit timer registers 1 and 2. tcl1 is set with an 8-bit memory manipulation instruction. reset input clears tcl1 to 00h. 215 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud figure 9-4. format of timer clock select register 1 caution when rewriting tcl1 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. ti1: 8-bit timer register 1 input pin 4. ti2: 8-bit timer register 2 input pin 5. mcs: bit 0 of oscillation mode select register (osms) 6. values in parentheses apply to operation with f x = 5.0 mhz tcl17 tcl16 tcl15 tcl14 tcl13 tcl12 tcl11 tcl10 76543210 symbol tcl1 ff41h 00h r/w address after reset r/w tcl13 tcl12 tcl11 tcl10 0 0 0 0 ti1 falling edge 0 0 0 1 ti1 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs = 1 8-bit timer register 1 count clock selection mcs = 0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) tcl17 tcl16 tcl15 tcl14 0 0 0 0 ti2 falling edge 0 0 0 1 ti2 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs = 1 8-bit timer register 2 count clock selection mcs = 0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) 216 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (2) 8-bit timer mode control register (tmc1) this register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer registers 1 and 2. tmc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc1 to 00h. figure 9-5. format of 8-bit timer mode control register 1 cautions 1. switch the operating mode after stopping timer operation. 2. when used as a 16-bit timer register (tms), tce1 should be used for operation enable/ stop. <0> <1> 2 3 4 5 6 7 symbol tce1 ff49h 00h r/w address after reset r/w tce2 tmc12 0 0 0 0 0 tmc1 tce1 8-bit timer register 1 operation control 0 operation stopped (tm1 is cleared to 0) 1 operation enabled tce2 8-bit timer register 2 operation control operation stopped (tm2 is cleared to 0) operation enabled 0 1 tmc12 operating mode selection 8-bit timer register 2-channel mode (tm1, tm2) 16-bit timer register 1-channel mode (tms) 0 1 217 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (3) 8-bit timer output control register (toc1) this register controls operation of 8-bit timer/event counter output controllers 1 and 2. it sets/resets the r-s flip-flops (lv1 and lv2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. toc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears toc1 to 00h. figure 9-6. format of 8-bit timer output control register cautions 1. be sure to set toc1 after stopping timer operation. 2. after data setting, 0 is read from lvs1, lvs2, lvr1, and lvr2 when they are read. <0> 1 <2> <3> <4> 5 <6> <7> symbol toe1 toc11 lvr1 lvs1 toe2 toc15 lvr2 lvs2 toc1 ff4fh 00h r/w address after reset r/w toe1 8-bit timer/event counter 1 outptut control 0 output disabled (port mode) 1 output enabled toc11 8-bit timer/event counter 1 timer output f/f control 0 inverted operation disabled 1 inverted operation enabled lvs1 lvr1 8-bit timer/event counter 1 timer output f/f status set 0 0 unchanged 0 1 timer output f/f is reset to 0 1 0 timer output f/f is set to 1 1 1 setting prohibited toe2 8-bit timer/event counter 2 output control 0 output disabled (port mode) 1 output enabled toc15 8-bit timer/event counter 2 timer output f/f control 0 inverted operation disabled 1 inverted operation enabled lvs2 lvr2 8-bit timer/event counter 2 timer output f/f status set 0 0 unchanged 0 1 timer output f/f is reset to 0 1 0 timer output f/f is set to 1 1 1 setting prohibited 218 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (4) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/to1 and p32/to2 pins for timer output, set pm31, pm32, and the output latches of p31 and p32 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 9-7. format of port mode register 3 0 1 2 3 4 5 6 7 symbol pm30 ff23h ffh r/w address after reset r/w pm31 pm32 pm33 pm34 pm35 pm36 pm37 pm3 pm3n p3n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 219 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.4 operations of 8-bit timer/event counters 1 and 2 9.4.1 8-bit timer/event counter mode (1) interval timer operations 8-bit timer/event counters 1 and 2 operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). when the count values of 8-bit timer registers 1 and 2 (tm1 and tm2) match the values set to cr10 and cr20, counting continues with the tm1 and tm2 values cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. the count clock of tm1 can be selected using bits 0 to 3 (tcl10 to tcl13) of timer clock select register 1 (tcl1). the count clock of tm2 can be selected using bits 4 to 7 (tcl14 to tcl17) of timer clock select register 1 (tcl1). for the operation when the value of the compare register is changed during a timer count operation, see 9.5 (3) operation after compare register change during timer count operation . figure 9-8. interval timer operation timing remark interval time = (n + 1) t : n = 00h to ffh count clock tm1 count value inttm1 cr10 to1 interval time interval time interval time interrupt request acknowledge interrupt request acknowledge n n n n count start clear clear t 00 01 n 00 01 n 00 01 n 220 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud table 9-6. interval time of 8-bit timer/event counter 1 tcl13 tcl12 tcl11 tcl10 minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 01102 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 s) (204.8 s) (400 ns) (800 ns) 01112 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (204.8 s) (409.6 s) (800 ns) (1.6 s) 10002 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (409.6 s) (819.2 s) (1.6 s) (3.2 s) 10012 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (819.2 s) (1.64 ms) (3.2 s) (6.4 s) 10102 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (1.64 ms) (3.28 ms) (6.4 s) (12.8 s) 10112 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (3.28 ms) (6.55 ms) (12.8 s) (25.6 s) 11002 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (6.55 ms) (13.1 ms) (25.6 s) (51.2 s) 11012 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (13.1 ms) (26.2 ms) (51.2 s) (102.4 s) 11102 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (26.2 ms) (52.4 ms) (102.4 s) (204.8 s) 11112 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (104.9 ms) (209.7 ms) (409.6 s) (819.2 s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. tcl10 to tcl13: bits 0 to 3 of timer clock select register 1 (tcl1) 4. values in parentheses apply to operation with f x = 5.0 mhz. 221 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud table 9-7. interval time of 8-bit timer/event counter 2 tcl17 tcl16 tcl15 tcl14 minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti2 input cycle 2 8 ti2 input cycle ti2 input edge cycle 0001 ti2 input cycle 2 8 ti2 input cycle ti2 input edge cycle 01102 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 s) (204.8 s) (400 ns) (800 ns) 01112 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (204.8 s) (409.6 s) (800 ns) (1.6 s) 10002 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (409.6 s) (819.2 s) (1.6 s) (3.2 s) 10012 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (819.2 s) (1.64 ms) (3.2 s) (6.4 s) 10102 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (1.64 ms) (3.28 ms) (6.4 s) (12.8 s) 10112 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (3.28 ms) (6.55 ms) (12.8 s) (25.6 s) 11002 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (6.55 ms) (13.1 ms) (25.6 s) (51.2 s) 11012 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (13.1 ms) (26.2 ms) (51.2 s) (102.4 s) 11102 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (26.2 ms) (52.4 ms) (102.4 s) (204.8 s) 11112 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (104.9 ms) (209.7 ms) (409.6 s) (819.2 s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. tcl14 to tcl17: bits 4 to 7 of timer clock select register 1 (tcl1) 4. values in parentheses apply to operation with f x = 5.0 mhz 222 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (2) external event counter operation the external event counter counts the number of external clock pulses to be input to the ti1/p33 and ti2/ p34 pins using 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 and tm2 are incremented each time the valid edge specified by the timer clock select register (tcl1) is input. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers 10 and 20 (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. figure 9-9. external event counter operation timing (with rising edge specified) remark n = 00h to ffh ti1 pin input tm1 count value inttm1 cr10 00 01 02 03 04 05 n 1 n 00 01 02 03 n 223 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (3) square-wave output operation 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (cr10 and cr20). the to1/p31 or to2/p32 pin output status is reversed at intervals of the count value preset to cr10 or cr20 by setting bit 0 (toe1) or bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-8. square-wave output ranges of 8-bit timer/event counters 1 and 2 minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 s) (204.8 s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (204.8 s) (409.6 s) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (409.6 s) (819.2 s) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (819.2 s) (1.64 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (1.64 ms) (3.28 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (3.28 ms) (6.55 ms) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (6.55 ms) (13.1 ms) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (13.1 ms) (26.2 ms) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (26.2 ms) (52.4 ms) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (104.9 ms) (209.7 ms) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 224 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud figure 9-10. square-wave output operation timing note the initial value of the to1 output can be set by bits 2 and 3 (lvs1 and lvr1) of the 8-bit timer output control register (toc1). count clock tm1 count value 01 02 00 n 1 n 00 01 02 n 1 n 00 count start cr10 n n to1 note 225 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.4.2 16-bit timer/event counter mode when bit 2 (tmc12) of the 8-bit timer mode control register (tmc1) is set to 1, the 16-bit timer/event counter mode is set. in this mode, the count clock is selected by using bits 0 to 3 (tcl10 to tcl13) of the timer clock select register (tcl1), and the overflow signal of 8-bit timer/event counter 1 (tm1) is used as the count clock for 8-bit timer/event counter 2 (tm2). the counting operation is enabled or disabled in this mode by using bit 0 (tce1) of tmc1. (1) operation as interval timer the 16-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at intervals of the count values set in advance to the 2 channels of the 8-bit compare registers (cr10 and cr20). when setting a count value, assign the value of the higher 8 bits to cr20 and the value of the lower 8 bits to cr10. for the count values that can be set (interval time), see table 9-9 . when the value of 8-bit timer register 1 (tm1) matches the value of cr10 and the value of 8-bit timer register 2 (tm1) matches the value of cr20, the values of tm1 and tm2 are cleared to 0, and at the same time, an interrupt request signal (inttm2) is generated. for the operation timing of the interval timer, see figure 9- 11 . select the count clock by using bits 0 to 3 (tcl10 to tcl13) of timer clock select register 1 (tcl1). the overflow signal of tm1 is used as the count clock for tm2. figure 9-11. interval timer operation timing remark interval time = (n + 1) t : n = 0000h to ffffh caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, an interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output controller 1 is inverted. thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledgment. when reading the 16-bit timer register (tms) count value, use a 16-bit memory manipulation instruction. count clock tms (tm1, tm2) count value cr10, cr20 inttm2 to2 interval time interval time interval time interrupt request acknowledge interrupt request acknowledge nn nn count start clear clear 0000 0001 n 0000 0001 n 0000 0001 n t 226 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud table 9-9. interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter tcl13 tcl12 tcl11 tcl10 minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 01102 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 01112 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 10002 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (104.9 ms) (209.7 ms) (1.6 s) (3.2 s) 10012 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (209.7 ms) (419.4 ms) (3.2 s) (6.4 s) 10102 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (419.4 ms) (838.9 ms) (6.4 s) (12.8 s) 10112 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (838.9 ms) (1.7 s) (12.8 s) (25.6 s) 11002 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (1.7 s) (3.4 s) (25.6 s) (51.2 s) 11012 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (3.4 s) (6.7 s) (51.2 s) (102.4 s) 11102 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (6.7 s) (13.4 s) (102.4 s) (204.8 s) 11112 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (26.8 s) (53.7 s) (409.6 s) (819.2 s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. tcl10 to tcl13: bits 0 to 3 of timer clock select register 1 (tcl1) 4. values in parentheses apply to operation with f x = 5.0 mhz. 227 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (2) external event counter operations the external event counter counts the number of external clock pulses to be input to the ti1/p33 pin using 2-channel 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 is incremented each time the valid edge specified by timer clock select register 1 (tcl1) is input. when tm1 overflows as a result, tm2 is incremented with the overflow signal used as its count clock. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers 10 and 20 (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signal (inttm2) is generated. figure 9-12. external event counter operation timing (with rising edge specified) caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, an interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output controller 1 is inverted. thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledgment. when reading the 16-bit timer register (tms) count value, use a 16-bit memory manipulation instruction. ti1 pin input tm1, tm2 count value cr10, cr20 inttm2 0000 0001 0002 0003 0004 0005 n 1 n 0000 0001 0002 0003 n 228 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (3) square-wave output operation 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (cr10 and cr20). to set a count value, set the value of the higher 8 bits to cr20, and the value of the lower 8 bits to cr10. the to2/p32 pin output status is reversed at intervals of the count value preset to cr10 and cr20 by setting bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-10. square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 s) (52.4 ms) (104.9 ms) (800 ns) (1.6 s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 s) (3.2 s) (104.9 ms) (209.7 ms) (1.6 s) (3.2 s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 s) (6.4 s) (209.7 ms) (419.4 ms) (3.2 s) (6.4 s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 s) (12.8 s) (419.4 ms) (838.9 ms) (6.4 s) (12.8 s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 s) (25.6 s) (838.9 ms) (1.7 s) (12.8 s) (25.6 s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 s) (51.2 s) (1.7 s) (3.4 s) (25.6 s) (51.2 s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 s) (102.4 s) (3.4 s) (6.7 s) (51.2 s) (102.4 s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 s) (204.8 s) (6.7 s) (13.4 s) (102.4 s) (204.8 s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 s) (819.2 s) (26.8 s) (53.7 s) (409.6 s) (819.2 s) remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) 3. values in parentheses apply to operation with f x = 5.0 mhz. 229 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud figure 9-13. square-wave output operation timing count clock tm1 01h n m n + 1 ffh ffh 00h 00h 02h m m 1 00h 01h 00h 00h ffh n 00h 01h 01h 00h n tm2 cr10 cr20 to2 interval time count start level inversion counter clear 230 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud 9.5 cautions on 8-bit timer/event counters 1 and 2 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer registers 1 and 2 (tm1 and tm2) are started asynchronously to the count pulse. figure 9-14. start timing of 8-bit timer registers 1 and 2 (2) 8-bit compare register 10 and 20 setting 8-bit compare registers 10 and 20 (cr10 and cr20) can be set to 00h. thus, when these 8-bit compare registers are used as event counters, a one-pulse count operation can be carried out. when the 8-bit compare register is used as 16-bit timer/event counter, write data to cr10 and cr20 after setting bit 0 (tce1) of the 8-bit timer mode control register (tmc1) and stopping timer operation. figure 9-15. external event counter operation timing count pulse tm1, tm2 count value 00h 01h 02h 03h 04h timer start ti1, ti2, input cr10, cr20 tm1, tm2 count value to1, to2 interrupt request flag 00h 00h 00h 00h 00h 231 chapter 9 8-bit timer/event counter user's manual u12013ej3v2ud (3) operation after compare register change during timer count operation if the values after 8-bit compare registers 10 and 20 (cr10 and cr20) are changed are smaller than those of the 8-bit timer registers (tm1 and tm2), tm1 and tm2 continue counting, overflow and then restart counting from 0. thus, if the value after cr10 and cr20 change (m) is smaller than value before the change (n), it is necessary to restart the timer after changing cr10 and cr20. figure 9-16. timing after compare register change during timer count operation remark n > x > m count pulse cr10, cr20 tm1, tm2 count value x 1 x ffh 00h 01h 02h m n 232 user's manual u12013ej3v2ud chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. watch timer interval timer the watch timer and the interval timer can be used simultaneously. (1) watch timer when the 32.768 khz subsystem clock is used, a flag (wtif) is set at 0.5-second or 0.25-second intervals. when the 4.19 mhz (standard: 4.194304 mhz) main system clock is used, a flag (wtif) is set at 0.5-second or 0.25-second intervals. caution 0.5-second intervals cannot be generated with the 5.0 mhz main system clock. switch to the 32.768 khz subsystem clock to generate 0.5-second intervals. remark f xx : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency (2) interval timer interrupt requests (inttm3) are generated at the preset time interval. table 10-1. interval timer interval time interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 2 4 1/f w 410 s 488 s 488 s 2 5 1/f w 819 s 977 s 977 s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f xx /2 7 or f xt ) 233 chapter 10 watch timer user's manual u12013ej3v2ud 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-2. watch timer configuration item configuration counter 5 bits 1 control registers timer clock select register 2 (tcl2) watch timer mode control register (tmc2) 10.3 watch timer control registers the following two registers are used to control the watch timer. timer clock select register 2 (tcl2) watch timer mode control register (tmc2) (1) timer clock select register 2 (tcl2) (see figure 10-2. ) this register sets the watch timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. remark besides setting the watch timer count clock, tcl2 sets the watchdog timer count clock and buzzer output frequency. 234 chapter 10 watch timer user's manual u12013ej3v2ud figure 10-1. watch timer block diagram tmc21 prescaler selector intwt 5-bit counter f w 2 14 f w 2 13 inttm3 to 16-bit timer/ event counter watch timer mode control register tmc26 tmc25 tmc24 tmc23 tmc22 tmc21 tmc20 internal bus tcl24 timer clock select register 2 3 f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w f xx /2 7 f xt clear clear selector selector selector 235 chapter 10 watch timer user's manual u12013ej3v2ud figure 10-2. format of timer clock select register 2 caution when changing the count clock, be sure to stop operation of the watch timer before rewriting tcl2 (stopping operation is not necessary when rewriting the same data). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don t care 5. mcs: bit 0 of oscillation mode select register (osms) 6. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 11 (2.4 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 12 (1.2 khz) watchdog timer count clock selection (see chapter 11 watchdog timer ) 0 1 tcl24 f xx /2 7 f xt (32.768 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disabled f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (see chapter 13 buzzer output controller ) mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 236 chapter 10 watch timer user's manual u12013ej3v2ud (2) watch timer mode control register (tmc2) this register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. tmc2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc2 to 00h. figure 10-3. format of watch timer mode control register caution when the watch timer is used, the prescaler should not be cleared frequently. remarks 1. f w : watch timer clock frequency (f xx /2 7 or f xt ) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. f xt : subsystem clock oscillation frequency 0 7 tmc26 6 tmc25 tmc24 4 tmc23 3210 ff4ah address tmc2 symbol tmc22 tmc21 tmc20 5 00h after reset r/w r/w 0 1 tmc23 f xx = 5.0 mhz operation 2 14 /f w (0.4 sec) 2 13 /f w (0.2 sec) watch flag set time selection 0 0 0 0 1 1 other than above 0 0 1 1 0 0 0 1 0 1 0 1 tmc26 tmc25 tmc24 f xx = 5.0 mhz operation 2 4 /f w (410 s) 2 5 /f w (819 s) 2 6 /f w (1.64 ms) 2 7 /f w (3.28 ms) 2 8 /f w (6.55 ms) 2 9 /f w (13.1 ms) setting prohibited f xx = 4.19 mhz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) f xt = 32.768 khz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) prescaler interval time selection f xx = 4.19 mhz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) f xt = 32.768 khz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) tmc22 0 1 5-bit counter operation control clear after operation stop operation enable tmc21 0 1 prescaler operation control clear after operation stop operation enable tmc20 0 1 watch operating mode selection normal operating mode (flag set at f w /2 14 ) fast feed operating mode (flag set at f w /2 5 ) 237 chapter 10 watch timer user's manual u12013ej3v2ud 10.4 watch timer operations 10.4.1 watch timer operation when the 32.768 khz subsystem clock or 4.19 mhz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. the watch timer sets the test input flag (wtif) to 1 at a constant time interval. when wtmk = 0, the standby state (stop mode/halt mode) can be cleared by setting wtif to 1. when bit 2 (tmc22) of the watch timer mode control register (tmc2) is cleared to 0, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be achieved by clearing tmc22 to 0 (maximum error: 26.2 ms when operated at f xx = 5.0 mhz). 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value. the interval time can be selected using bits 4 to 6 (tmc24 to tmc26) of the watch timer mode control register (tmc2). table 10-3. interval timer interval time tmc26 tmc25 tmc24 interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 0002 4 1/f w 410 s 488 s 488 s 0012 5 1/f w 819 s 977 s 977 s 0102 6 1/f w 1.64 ms 1.95 ms 1.95 ms 0112 7 1/f w 3.28 ms 3.91 ms 3.91 ms 1002 8 1/f w 6.55 ms 7.81 ms 7.81 ms 1012 9 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f xx /2 7 or f xt ) tmc24 to tmc26: bits 4 to 6 of watch timer mode control register (tmc2) 238 user's manual u12013ej3v2ud chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. watchdog timer interval timer caution select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (wdtm) (the watchdog timer and interval timer cannot be used at the same time). (1) watchdog timer mode an inadvertent program loop is detected. upon detection of the program loop, a non-maskable interrupt request or reset can be generated. table 11-1. watchdog timer program loop detection times runaway detection time mcs = 1 mcs = 0 2 11 1/f xx 2 11 1/f x (410 s) 2 12 1/f x (819 s) 2 12 1/f xx 2 12 1/f x (819 s) 2 13 1/f x (1.64 ms) 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz. 239 chapter 11 watchdog timer user's manual u12013ej3v2ud (2) interval timer mode interrupt requests are generated at the preset time intervals. table 11-2. interval times interval time mcs = 1 mcs = 0 2 11 1/f xx 2 11 1/f x (410 s) 2 12 1/f x (819 s) 2 12 1/f xx 2 12 1/f x (819 s) 2 13 1/f x (1.64 ms) 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz. 240 chapter 11 watchdog timer user's manual u12013ej3v2ud 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-3. watchdog timer configuration item configuration control registers timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) figure 11-1. watchdog timer block diagram prescaler f xx 2 4 f xx 2 5 f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 selector watchdog timer mode register internal bus internal bus tcl22 tcl21 tcl20 f xx /2 3 f xx 2 11 timer clock select register 2 3 wdtm4 wdtm3 8-bit counter tmmk4 run tmif4 intwdt maskable interrupt request intwdt non-maskable interrupt request reset controller run 241 chapter 11 watchdog timer user's manual u12013ej3v2ud 11.3 watchdog timer control registers the following two registers are used to control the watchdog timer. timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) (1) timer clock select register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. remark besides setting the watchdog timer count clock, tcl2 sets the watch timer count clock and buzzer output frequency. 242 chapter 11 watchdog timer user's manual u12013ej3v2ud figure 11-2. format of timer clock select register 2 caution changing the count clock (rewriting tcl20 to tcl22) after watchdog timer operation has started is prohibited. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don t care 5. mcs: bit 0 of oscillation mode select register (osms) 6. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs = 1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs = 0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs = 1 f x /2 7 (39.1 khz) mcs = 0 f x /2 8 (19.5 khz) watch timer count clock selection (see chapter 10 watch timer ) 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs = 1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (see chapter 13 buzzer output controller ) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz) 243 chapter 11 watchdog timer user's manual u12013ej3v2ud (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 11-3. format of watchdog timer mode register notes 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. the watchdog timer starts operating as an interval timer as soon as run has been set to 1. 3. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. cautions 1. when run is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by timer clock select register 2 (tcl2). 2. to use watchdog timer modes 1 and 2, make sure that the interrupt request flag (tmif4) is 0, and then set wdtm4 to 1. if wdtm4 is set to 1 when tmif4 is 1, the non-maskable interrupt request occurs, regardless of the contents of wdtm3. remark : don t care rum <7> 0 6 0 wdtm4 4 wdtm3 3210 fff9h address wdtm symbol 000 5 00h after reset r/w r/w run 0 1 watchdog timer operation mode selection note 3 count stop counter is cleared and counting starts. wdtm3 0 1 watchdog timer operation mode selection selection note 1 interval timer mode note 2 (maskable interrupt request occurs upon generation of an overflow.) watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of an overflow.) watchdog timer mode 2 (reset operation is activated upon generation of an overflow.) wdtm4 0 1 1 244 chapter 11 watchdog timer user's manual u12013ej3v2ud 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer operates to detect an inadvertent program loop. the watchdog timer count clock (program loop detection time interval) can be selected using bits 0 to 2 (tcl20 to tcl22) of timer clock select register 2 (tcl2). the watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set loop detection time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the program loop detection time has elapsed, system reset or a non-maskable interrupt request is generated according to the value of wdtm bit 3 (wdtm3). by setting run to 1, the watchdog timer can be cleared. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual loop detection time may be shorter than the set time by a maximum of 0.5%. 2. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-4. watchdog timer program loop detection time tcl22 tcl21 tcl20 runaway detection time mcs = 1 mcs = 0 0002 11 1/f xx 2 11 1/f x (410 s) 2 12 1/f x (819 s) 0012 12 1/f xx 2 12 1/f x (819 s) 2 13 1/f x (1.64 ms) 0102 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 0112 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 1002 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 1012 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 1102 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 1112 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. tcl20 to tcl22: bits 0 to 2 of timer clock select register 2 (tcl2) 5. values in parentheses apply to operation with f x = 5.0 mhz. 245 chapter 11 watchdog timer user's manual u12013ej3v2ud 11.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is cleared to 0. the count clock (interval time) can be selected by bits 0 to 2 (tcl20 to tcl22) of timer clock select register 2 (tcl2). by setting bit 7 (run) of wdtm to 1, the watchdog timer starts operating as an interval timer. when the watchdog timer operates as interval timer, the interrupt mask flag (tmmk4) and priority specification flag (tmpr4) are validated and a maskable interrupt request (intwdt) can be generated. among the maskable interrupt requests, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set bit 7 (run) of wdtm to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting by wdtm may be shorter than the set time by a maximum of 0.5%. 3. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-5. interval timer interval time tcl22 tcl21 tcl20 interval time mcs = 1 mcs = 0 0002 11 1/f xx 2 11 1/f x (410 s) 2 12 1/f x (819 s) 0012 12 1/f xx 2 12 1/f x (819 s) 2 13 1/f x (1.64 ms) 0102 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 0112 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 1002 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 1012 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 1102 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 1112 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. tcl20 to tcl22: bits 0 to 2 of timer clock select register 2 (tcl2) 5. values in parentheses apply to operation with f x = 5.0 mhz. 246 user's manual u12013ej3v2ud chapter 12 clock output controller 12.1 clock output controller functions the clock output controller is used for carrier output during remote controlled transmission and clock output for supply to peripheral lsi devices. the clock selected by timer clock select register 0 (tcl0) is output from the pcl/ p35 pin. follow the procedure below to output clock pulses. (1) select the clock pulse output frequency (with clock pulse output disabled) using bits 0 to 3 (tcl00 to tcl03) of tcl0. (2) set the p35 output latch to 0. (3) set bit 5 (pm35) of port mode register 3 (pm3) to 0 (set to output mode). (4) set bit 7 (cloe) of timer clock select register 0 (tcl0) to 1. caution clock output cannot be used when the p35 output latch is set to 1. remark when clock output enable/disable is switched, the clock output controller does not output pulses with small widths (see the portions marked with * in figure 12-1 ). figure 12-1. remote controlled output application example cloe pcl/p35 pin output ** 247 chapter 12 clock output controller user's manual u12013ej3v2ud 12.2 clock output controller configuration the clock output controller consists of the following hardware. table 12-1. clock output controller configuration item configuration control registers timer clock select register 0 (tcl0) port mode register 3 (pm3) figure 12-2. clock output controller block diagram 12.3 clock output function control registers the following two registers are used to control the clock output function. timer clock select register 0 (tcl0) port mode register 3 (pm3) (1) timer clock select register 0 (tcl0) this register sets the pcl output clock. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tcl0 to 00h. remark besides setting the pcl output clock, tcl0 sets the 16-bit timer register count clock. internal bus f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt cloe tcl03 tcl02 tcl01 tcl00 p35 output latch synchronizing circuit 4 pm35 selector timer clock select register 0 port mode register 3 pcl /p35 248 chapter 12 clock output controller user's manual u12013ej3v2ud figure 12-3. format of timer clock select register 0 cautions 1. the ti00/p00/intp0 pin valid edge is set by external interrupt mode register 0 (intm0), and the sampling clock frequency is selected by the sampling clock select register (scs). 2. when enabling pcl output, set tcl00 to tcl03, then set cloe to 1 with a 1-bit memory manipulation instruction. 3. when reading the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from the 16-bit capture/compare register (cr01). 4. when rewriting tcl0 to other data, stop the clock operation beforehand. cloe <7> tcl06 6 tcl05 tcl04 4 tcl03 3210 ff40h address tcl0 symbol tcl02 tcl01 tcl00 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 1 other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 tcl03 tcl02 tcl01 f xt (32.768 khz) f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 setting prohibited mcs = 1 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) mcs = 0 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) pcl output clock selection cloe 0 1 pcl output control output disabled output enabled 0 0 0 0 1 1 other than above 0 0 1 1 0 1 0 1 0 1 0 1 tcl06 tcl05 tcl04 ti00 (valid edge specifiable) 2f xx f xx f xx /2 f xx /2 2 watch timer output (inttm3) setting prohibited mcs = 1 setting prohibited f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) mcs = 0 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 16-bit timer register count clock selection tcl00 0 1 0 1 0 1 0 1 0 249 chapter 12 clock output controller user's manual u12013ej3v2ud remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00: 16-bit timer/event counter input pin 5. tm0: 16-bit timer register 6. mcs: bit 0 of oscillation mode select register (osms) 7. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p35/pcl pin for clock output, set pm35 and the output latch of p35 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 12-4. format of port mode register 3 pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 250 user's manual u12013ej3v2ud chapter 13 buzzer output controller 13.1 buzzer output controller functions the buzzer output controller outputs 1.2 khz, 2.4 khz, 4.9 khz, or 9.8 khz frequency square waves. the buzzer frequency selected by timer clock select register 2 (tcl2) is output from the buz/p36 pin. follow the procedure below to output the buzzer frequency. (1) select the buzzer output frequency using bits 5 to 7 (tcl25 to tcl27) of tcl2. (2) set the p36 output latch to 0. (3) set bit 6 (pm36) of port mode register 3 (pm3) to 0 (set to output mode). caution buzzer output cannot be used when the p36 output latch is set to 1. 13.2 buzzer output controller configuration the buzzer output controller consists of the following hardware. table 13-1. buzzer output controller configuration item configuration control registers timer clock select register 2 (tcl2) port mode register 3 (pm3) figure 13-1. buzzer output controller block diagram internal bus f xx /2 9 f xx /2 10 f xx /2 11 tcl27 tcl26 tcl25 3 pm36 selector timer clock select register 2 port mode register 3 buz/p36 p36 output latch 251 chapter 13 buzzer output controller user's manual u12013ej3v2ud 13.3 buzzer output function control registers the following two registers are used to control the buzzer output function. timer clock select register 2 (tcl2) port mode register 3 (pm3) (1) timer clock select register 2 (tcl2) this register sets the buzzer output frequency. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. remark besides setting the buzzer output frequency, tcl2 sets the watch timer count clock and the watchdog timer count clock. 252 chapter 13 buzzer output controller user's manual u12013ej3v2ud figure 13-2. format of timer clock select register 2 cautions 1. be sure to stop operation of the watch timer or buzzer to be changed before rewriting tcl2 (stop operation is not necessary when rewriting the same data). the operation is stopped by the following methods. ? buzzer output: input 0 to bit 7 of tcl2 (tcl27) ? watch timer: input 0 to bit 2 (tmc22) of watch timer mode control register 2 (tmc2) 2. changing the count clock (rewriting tcl20 to tcl22) after watchdog timer operation has started is prohibited. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don? care 5. mcs: bit 0 of oscillation mode select register (osms) 6. values in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs = 1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs = 0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection (see chapter 11 watchdog timer ) 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs = 1 f x /2 7 (39.1 khz) mcs = 0 f x /2 8 (19.5 khz) watch timer count clock selection (see chapter 10 watch timer ) 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disabled f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs = 1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz) 253 chapter 13 buzzer output controller user's manual u12013ej3v2ud (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p36/buz pin for buzzer output, clear pm36 and the output latch of p36 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 13-3. format of port mode register 3 pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 254 user's manual u12013ej3v2ud chapter 14 a/d converter 14.1 a/d converter functions the a/d converter converts an analog input into a digital value. it consists of 8 channels (ani0 to ani7) with an 8-bit resolution. the conversion method is based on successive approximation and the conversion result is held in the 8-bit a/d conversion result register (adcr). a/d conversion can be started in the following two ways. (1) hardware start conversion is started by trigger input (intp3). (2) software start conversion is started by setting the a/d converter mode register (adm). one analog input channel is selected from ani0 to ani7 and a/d conversion is carried out. in the case of hardware start, a/d conversion stops when an a/d conversion operation ends, and an interrupt request (intad) is generated. in the case of software start, a/d conversion is repeated. each time an a/d conversion operation ends, an interrupt request (intad) is generated. 14.2 a/d converter configuration the a/d converter consists of the following hardware. table 14-1. a/d converter configuration item configuration analog inputs 8 channels (ani0 to ani7) control registers a/d converter mode register (adm) a/d converter input select register (adis) external interrupt mode register 1 (intm1) registers successive approximation register (sar) a/d conversion result register (adcr) 255 chapter 14 a/d converter user's manual u12013ej3v2ud figure 14-1. a/d converter block diagram notes 1. selector to select the number of channels to be used for analog input. 2. selector to select the channel for a/d conversion. 3. es40, es41: bits 0 and 1 of external interrupt mode register 1 (intm1) ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 selector a /d converter mode register 3 trigger enable es40, es41 note 3 sample & hold circuit 3 cs adis3 4 internal bus internal bus edge detector controller series resistor string (also functions as analog power supply) voltage comparator tap selector intad intp3 successive approximation register (sar) a / d converter input select register adis2 adis1 adis0 note 1 note 2 adm1 to adm3 intp3/p03 trg fr1 fr0 adm3 adm2 adm1 a/d conversion result register (adcr) av ref0 av ss selector hsc av ss 256 chapter 14 a/d converter user's manual u12013ej3v2ud (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to the a/d conversion result register (adcr). (2) a/d conversion result register (adcr) this register holds the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register (sar). adcr is read with an 8-bit memory manipulation instruction. reset input makes adcr undefined. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref0 and av ss , and generates a voltage to be compared with the analog input. (6) ani0 to ani7 pins these are 8-channel analog input pins to input analog signals to undergo a/d conversion to the a/d converter. pins other than those selected as analog input by the a/d converter input select register (adis) can be used as i/o ports. cautions 1. use the ani0 to ani7 input voltages within the specified range. if a voltage higher than or equal to av ref0 or lower than or equal to av ss is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. the analog input pins (ani0 to ani7) also function as i/o port pins (port 1). when a/d conversion is performed with any of pins ani0 to ani7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtained due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. 257 chapter 14 a/d converter user's manual u12013ej3v2ud (7) av ref0 pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref0 and av ss . the current flowing in the series resistor string can be reduced by setting the voltage to be input to the av ref0 pin to av ss level in standby mode. this pin also serves as an analog power supply pin. supply power to this pin when the a/d converter is used. caution a series resistor string of approximately 10 k ? is connected between the av ref0 pin and av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between av ref0 pin and the av ss pin, resulting in a large reference voltage error. (8) av ss pin this is a gnd potential pin of the a/d converter. keep it at the same potential as the v ss0 pin when not using the a/d converter. 258 chapter 14 a/d converter user's manual u12013ej3v2ud 14.3 a/d converter control registers the following three registers are used to control the a/d converter. a/d converter mode register (adm) a/d converter input select register (adis) external interrupt mode register 1 (intm1) (1) a/d converter mode register (adm) this register sets the analog input channel for a/d conversion, conversion time, conversion start/stop and external trigger. adm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm to 01h. 259 chapter 14 a/d converter user's manual u12013ej3v2ud figure 14-2. format of a/d converter mode register notes 1. set so that the a/d conversion time is 16 s or more. 2. setting is prohibited because the a/d conversion time is less than 16 s with f x set to this condition. cautions 1. the following sequence is recommended for reducing the power consumption of the a/d converter when the standby function is used: clear bit 7 (cs) to 0 first to stop the a/d conversion operation, and then execute the halt or stop instruction. 2. when restarting a stopped a/d conversion operation, start the a/d conversion operation after clearing the interrupt request flag (adif) to 0. remarks 1. f x : main system clock oscillation frequency 2. mcs: bit 0 of oscillation mode select register (osms) cs <7> trg <6> fr1 fr0 4 adm3 3210 ff80h address adm symbol adm2 adm1 hsc 5 01h after reset r/w r/w adm3 0 0 0 0 1 1 1 1 adm2 0 0 1 1 0 0 1 1 adm1 0 1 0 1 0 1 0 1 analog input channel selection ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 trg 0 1 external trigger selection no external trigger (software starts) conversion started by external trigger (hardware starts) fr1 0 0 1 1 fr0 0 1 0 0 other than above a/d conversion time selection note 1 f x = 5.0 mhz operation mcs = 1 80/f x ( 16.0 s ) 40/f x ( setting prohibited note 2 ) 50/f x ( setting prohibited note 2 ) 100/f x (20.0 s) setting prohibited mcs = 0 160/f x (32.0 s) 80/f x ( 16.0 s ) 100/f x (20.0 s) 200/f x (40.0 s) f x = 4.19 mhz operation mcs = 1 80/f x (19.1 s) 40/f x ( setting prohibited note 2 ) 50/f x ( setting prohibited note 2 ) 100/f x (23.8 s) mcs = 0 160/f x (38.1 s) 80/f x (19.1 s) 100/f x (23.8 s) 200/f x (47.7 s) cs 0 1 a/d conversion operation control operation stop operation start hsc 1 1 0 1 260 chapter 14 a/d converter user's manual u12013ej3v2ud (2) a/d converter input select register (adis) this register determines whether the ani0/p10 to ani7/p17 pins should be used for analog input channels or ports. pins other than those selected as analog input can be used as i/o ports. adis is set with an 8-bit memory manipulation instruction. reset input clears adis to 00h. cautions 1. set the analog input channel using the following procedure. (1) set the number of analog input channels using adis. (2) using the a/d converter mode register (adm), select one channel to undergo a/d conversion from among the channels set to analog input by adis. 2. no internal pull-up resistor can be used for the channels set to analog input by adis, irrespective of the value of bit 1 (puo1) of pull-up resistor option register l (puol). figure 14-3. format of a/d converter input select register 0 7 0 6 00 4 adis3 3210 ff84h address adis symbol adis2 adis1 adis0 5 00h after reset r/w r/w adis3 0 0 0 0 0 0 0 0 1 other than above number of analog input channel selection no analog input channel (p10 to p17) 1 channels (ani0, p11 to p17) 2 channels (ani0, ani1, p12 to p17) 3 channels (ani0 to ani2, p13 to p17) 4 channels (ani0 to ani3, p14 to p17) 5 channels (ani0 to ani4, p15 to p17) 6 channels (ani0 to ani5, p16, p17) 7 channels (ani0 to ani6, p17) 8 channels (ani0 to ani7) setting prohibited adis2 0 0 0 0 1 1 1 1 0 adis1 0 0 1 1 0 0 1 1 0 adis0 0 1 0 1 0 1 0 1 0 261 chapter 14 a/d converter user's manual u12013ej3v2ud (3) external interrupt mode register 1 (intm1) this register sets the valid edge for intp3 to intp5. intm1 is set with an 8-bit memory manipulation instruction. reset input clears intm1 to 00h. figure 14-4. format of external interrupt mode register 1 0 7 0 6 es61 es60 4 es51 3210 ffedh address intm1 symbol es50 es41 es40 5 00h after reset r/w r/w es41 0 0 1 1 es40 0 1 0 1 intp3 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es51 0 0 1 1 es50 0 1 0 1 intp4 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es61 0 0 1 1 es60 0 1 0 1 intp5 valid edge selection falling edge rising edge setting prohibited both rising and falling edges 262 chapter 14 a/d converter user's manual u12013ej3v2ud 14.4 a/d converter operations 14.4.1 basic operations of a/d converter (1) set the number of analog input channels using the a/d converter input select register (adis). (2) from among the analog input channels set by adis, select one channel for a/d conversion using the a/d converter mode register (adm). (3) sample the voltage input to the selected analog input channel using the sample & hold circuit. (4) sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until the end of a/d conversion. (5) bit 7 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref0 by the tap selector. (6) the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref0 , the msb of sar remains set. if the input is smaller than (1/2) av ref0 , the msb is reset. (7) next, bit 6 of sar is automatically set and the operation proceeds to the next comparison. in this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. bit 7 = 1: (3/4) av ref0 bit 7 = 0: (1/4) av ref0 the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated with the result as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 (8) comparison of this sort continues up to bit 0 of sar. (9) upon completion of the comparison of 8 bits, a valid digital result remains in sar and that value is transferred to and latched in the a/d conversion result register (adcr). at the same time, the a/d conversion end interrupt request (intad) can also be generated. 263 chapter 14 a/d converter user's manual u12013ej3v2ud figure 14-5. a/d converter basic operation a/d conversion operations are performed continuously until bit 7 (cs) of the ad converter mode register (adm) is reset to 0 by software. reset input makes adcr undefined. check the completion of a/d conversion by using the a/d conversion end interrupt request flag (adif). table 14-2. a/d converter sampling time and a/d conversion start delay time fr01 fr00 hs0c conversion time note 1 sampling time a/d conversion start delay time mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0 0 1 80/f x (16.0 s) 160/f x (32.0 s) 9/f x 18/f x 6/f x 12/f x 0 1 1 40/f x (setting prohibited note 2 ) 80/f x (16.0 s) 4.5/f x 9/f x 3/f x 6/f x 1 0 0 50/f x (setting prohibited note 2 ) 100/f x (20.0 s) 5.25/f x 10.5/f x 4.5/f x 9/f x 1 0 1 100/f x (20.0 s) 200/f x (40.0 s) 10.5/f x 21/f x 9/f x 18/f x other than above setting prohibited notes 1. set so that the a/d conversion time is 16 s or more. 2. setting is prohibited because the a/d conversion time is less than 16 s with f x set to this condition. remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 5.0 mhz. conversion time a/d converter operation undefined 80h c0h or 40h sar adcr intad conversion result sampling time cs = 0 1, or external trigger, or adm rewrite sampling a/d conversion conversion result a/d conversion start delay time cs 264 chapter 14 a/d converter user's manual u12013ej3v2ud 14.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (the value stored in the a/d conversion result register (adcr)) is shown by the following expression. adcr = int ( 256 + 0.5) or (adcr 0.5) v in < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses. v in : analog input voltage av ref0 :av ref0 pin voltage adcr value of a/d conversion result register (adcr) figure 14-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 14-6. relationship between analog input voltage and a/d conversion result v in av ref0 av ref0 256 av ref0 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion results (adcr) input voltage/av ref0 265 chapter 14 a/d converter user's manual u12013ej3v2ud 14.4.3 a/d converter operating mode one analog input channel is selected from among ani0 to ani7 by the a/d converter input select register (adis) and a/d converter mode register (adm) and a/d conversion is started. a/d conversion can be stared in the following two ways. hardware start: conversion is started by trigger input (intp3). software start: conversion is started by setting adm. the a/d conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg) and bit 7 (cs) of the a/d converter mode register (adm) are set to 1, the a/d conversion standby state is set. when the external trigger signal (intp3) is input, the a/d conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (adm1 to adm3) of adm. upon termination of a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends the a/d conversion operation and waits for a new external trigger signal to be input. when the external trigger input signal is input again, a/d conversion is carried out from the beginning. if data with cs cleared to 0 is written to adm during a/d conversion, the a/d conversion operation stops immediately. figure 14-7. a/d conversion by hardware start remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 adm rewrite cs = 1, trg = 1 standby state anin intp3 a /d conversion adcr intad anin anin anin anim anim anin anin standby state standby state adm rewrite cs = 1, trg = 1 anim anim anim 266 chapter 14 a/d converter user's manual u12013ej3v2ud (2) a/d conversion operation in software start when bit 6 (trg) and bit 7 (cs) of the a/d converter mode register (adm) are set to 0 and 1, respectively, a/d conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (adm1 to adm3) of adm. upon termination of a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, the next a/d conversion operation starts immediately. the a/d conversion operation continues repeatedly until new data is written to adm. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends the a/d conversion operation and starts a/d conversion on the newly written data. if data with cs cleared to 0 is written to adm during a/d conversion, the a/d conversion operation stops immediately. figure 14-8. a/d conversion by software start remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 conversion start cs = 1, trg = 0 a /d conversion adcr intad anin anin anim anin anim anim anin anin adm rewrite cs = 1, trg = 0 adm rewrite cs = 0, trg = 0 conversion suspended conversion results are not stored. stop 267 chapter 14 a/d converter user's manual u12013ej3v2ud 14.5 how to read the a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 8 bits, 1lsb = 1/2 8 = 1/256 = 0.4%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale offset, full-scale offset, integral linearity error, differential linearity error and errors which are combinations of these express the overall error. note that the quantization error is not included in the overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale offset, full-scale offset, integral linearity error, and differential linearity error in the characteristics table. figure 14-9. overall error figure 14-10. quantization error ideal line 0 0 1 1 digital output overall error analo g input av ref0 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input av ref0 0 268 chapter 14 a/d converter user's manual u12013ej3v2ud (4) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. the sampling time is included in the conversion time in the characteristics table. (5) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time 269 chapter 14 a/d converter user's manual u12013ej3v2ud 14.6 a/d converter cautions (1) power consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (cs) of the a/d converter mode register (adm) to 0). figure 14-11 shows how to reduce the current consumption in the standby mode. figure 14-11. example of method of reducing current consumption in standby mode (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage of av ref0 or above or av ss or below is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined. the conversion values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon end of conversion adcr read is given priority. after the read operation, the new conversion result is written to adcr. <2> conflict between adcr write and external trigger signal input upon end of conversion the external trigger signal is not acknowledged during a/d conversion. therefore, the external trigger signal is not acknowledged during adcr write. <3> conflict between adcr write and a/d converter mode register (adm) write or a/d converter input select register (adis) write adm or adis write is given priority. adcr write is not performed, nor is the conversion end interrupt request signal (intad) generated. av ref0 av ss p-ch series resistor string cs 270 chapter 14 a/d converter user's manual u12013ej3v2ud (4) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on the av ref0 and ani0 to ani7 pins. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 14-12 in order to reduce noise. figure 14-12. analog input pin handling (5) ani0/p10 to ani7/p17 pins the analog input pins ani0 to ani7 also function as i/o port pins (port 1). when a/d conversion is performed with any of pins ani0 to ani7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 14-12). (7) av ref0 pin input impedance a series resistor string of approximately 10 k ? is connected between the av ref0 pin and the av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the av ref0 pin and the av ss pin, and there will be a large reference voltage error. ani0 to ani7 av ref0 reference voltage input c = 100 to 1,000 pf if there is possibility that noise whose level is av ref0 or higher or av ss or lower may enter, clamp with a diode with a small v f (0.3 v or less). v dd0 av ss v ss0 271 chapter 14 a/d converter user's manual u12013ej3v2ud (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the a/d converter mode register (adm) is changed. caution is therefore required since, if a change of analog input pin is performed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the adm rewrite. at this time, when adif is read immediately after the adm rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before it is resumed. figure 14-13. a/d conversion end interrupt request generation timing remark n = 0, 1, ..., 7 m = 0, 1, ..., 7 (9) conversion result immediately after a/d converter start the first a/d conversion value immediately after a/d conversion is started may not satisfy ratings. therefore, implement a countermeasure such as polling a/d conversion end interrupt requests (intad) to delete the first conversion result. a /d conversion adcr intad anin anin anim anim anin anin anim anim adm rewrite (start of anin conversion) adm rewrite (start of anim conversion) adif is set but anim conversion has not ended. 272 chapter 14 a/d converter user's manual u12013ej3v2ud (10) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict with each other. therefore, read the a/d conversion result during the a/d conversion operation. to read the conversion result after stopping the a/d conversion operation, be sure to stop the a/d conversion before the next conversion ends. figures 14-14 and 14-15 show the timing of reading the conversion result. figure 14-14. timing of reading conversion result (when conversion result is undefined) figure 14-15. timing of reading conversion result (when conversion result is normal) (11) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss and v ss0 at one location on the board where the voltages are stable. normal conversion result undefined value a/d conversion ends a/d conversion ends normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr intad cs normal conversion result a/d conversion ends normal conversion result is read. a/d conversion is stopped. adcr intad cs 273 chapter 14 a/d converter user's manual u12013ej3v2ud (12) av ref0 pin connect a capacitor to the av ref0 pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and then is started, the voltage applied to the av ref0 pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref0 pin. figure 14-16 shows an example of connecting a capacitor. capacitor c1 is effective for noise of low frequency and capacitor c2 is effective for noise of high frequency. figure 14-16. example of connecting capacitor to av ref0 pin remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible. (13) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 14-17 shows the internal equivalent circuit of the ani0 to ani7 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the ani0 to ani7 pins. an example of this is shown in figure 14-18. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a low-pass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. av ref0 av ss c 2 c 1 274 chapter 14 a/d converter user's manual u12013ej3v2ud figure 14-17. internal equivalent circuit of pins ani0 to ani7 remark n = 0 to 7 table 14-3. resistances and capacitances of equivalent circuit (reference values) av ref0 r1 r2 c1 c2 c3 1.8 v 75 k ? 30 k ? 8 pf 4 pf 2 pf 2.7 v 12 k ? 8 k ? 8 pf 3 pf 2 pf 4.5 v 4 k ? 2.7 k ? 8 pf 1.4 pf 2 pf caution the resistances and capacitances in table 14-3 are not guaranteed values. figure 14-18. example of connection if signal source impedance is high remark n = 0 to 7 c3 c2 r2 r1 c1 anin c3 c2 r2 r1 275 user's manual u12013ej3v2ud chapter 15 d/a converter 15.1 d/a converter functions the d/a converter converts a digital input into an analog value. the d/a converter used is a 2-channel 8-bit resolution voltage output type d/a converter. the conversion method used is the r-2r resistor ladder method. start d/a conversion by setting bits 0 and 1 (dace0 and dace1) of the d/a converter mode register (dam). there are two modes for the d/a converter, as follows. (1) normal mode outputs an analog voltage signal immediately after d/a conversion. (2) real-time output mode outputs an analog voltage signal synchronously with the output trigger after d/a conversion. since a sine wave can be generated in this mode, it is useful for an msk modem for cordless telephone sets. 276 chapter 15 d/a converter user's manual u12013ej3v2ud 15.2 d/a converter configuration the d/a converter consists of the following hardware. table 15-1. d/a converter configuration item configuration registers d/a conversion value set register 0 (dacs0) d/a conversion value set register 1 (dacs1) control register d/a converter mode register (dam) figure 15-1. d/a converter block diagram selector d/a conversion value set register 1 (dacs1) internal bus internal bus 2r 2r 2r 2r r r 2r 2r 2r 2r r r dam5 ano1/p131 ano0/p130 d/a converter mode register dacs1 write inttm2 dacs0 write inttm1 av ref1 av ss d/a conversion value set register 0 (dacs0) dam4 dace1 dace0 selector 277 chapter 15 d/a converter user's manual u12013ej3v2ud (1) d/a conversion value set registers 0, 1 (dacs0, dacs1) dacs0 and dacs1 are registers that set the values used to determine the analog voltages to be output to the ano0 and ano1 pins, respectively. dacs0 and dacs1 are set with an 8-bit memory manipulation instruction. reset input clears dacs0 and dacs1 to 00h. analog voltage output to the ano0 and ano1 pins is determined by the following expression. anon output voltage = av ref1 where, n = 0, 1 cautions 1. in the real-time output mode, when data that is set in dacs0 and dacs1 is read before an output trigger is generated, the previous data is read rather than the set data. 2. in the real-time output mode, data should be set to dacs0 and dacs1 after an output trigger and before the next output trigger. dacsn 256 278 chapter 15 d/a converter user's manual u12013ej3v2ud 15.3 d/a converter control registers the d/a converter mode register (dam) controls the d/a converter. this register sets d/a converter operation enable/stop. dam is set with a 1-bit or an 8-bit memory manipulation instruction. reset input clears dam to 00h. figure 15-2. format of d/a converter mode register cautions 1. when using the d/a converter, alternate-function port pins should be set to the input mode, and pull-up resistors should be disconnected. 2. always set bits 2, 3, 6, and 7 to 0. 3. when d/a conversion is stopped, the output state is high-impedance. 4. the output triggers are inttm1 and inttm2 for channel 0 and channel 1, respectively, in the real-time output mode. 0 7 0 6 dam5 dam4 4 0 3 2 <1> <0> ff98h address dam symbol 0 dace1 dace0 5 00h after reset r/w r/w dam5 0 1 normal mode real-time output mode dace0 0 1 d/a conversion stop d/a conversion enable dace1 0 1 d/a conversion stop d/a conversion enable dam4 0 1 normal mode real-time output mode d/a converter channel 0 control d/a converter channel 1 control d/a converter channel 0 operating mode d/a converter channel 1 operating mode 279 chapter 15 d/a converter user's manual u12013ej3v2ud 15.4 d/a converter operations (1) the channel 0 operating mode and channel 1 operating mode are selected by bits 4 and 5 (dam4 and dam5), respectively, of the d/a converter mode register (dam). (2) set the data corresponding to the analog voltages output to the ano0/p130 and ano1/p131 pins to d/a conversion value setting registers 0 and 1 (dacs0 and dacs1), respectively. (3) d/a conversion of channel 0 or channel 1 can be started by setting bits 0 or 1 (dace0 or dace1) of dam, respectively. (4) in the normal mode, the analog voltage signals are output to the ano0/p130 and ano1/p131 pins immediately after d/a conversion. in the real-time output mode, the analog voltage signals are output synchronously with the output triggers. (5) in the normal mode, the analog voltage signals to be output are held until new data is set in dacs0 and dacs1. in the realtime output mode, new data is set in dacs0 and dacs1 and then held until the next trigger is generated. caution set dace0 and dace1 after setting data in dacs0 and dacs1. 280 chapter 15 d/a converter user's manual u12013ej3v2ud 15.5 d/a converter cautions (1) output impedance of d/a converter because the output impedance of the d/a converter is high, use of current flowing from the anon pins (n = 0,1) is prohibited. if the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the anon pins. in addition, wiring from the anon pins to the buffer amplifier or the load should be as short as possible (because of high output impedance). if the wiring may be long, design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring. figure 15-3. use example of buffer amplifier (a) inverting amplifier (b) voltage-follower (2) output voltage of d/a converter because the output voltage of the converter changes in steps, use the d/a converter output signals in general by connecting a low-pass filter. (3) av ref1 pin when only one of the d/a converter channels is used with av ref1 < v dd0 , the other pins that are not used as analog outputs must be set as follows: set the pm13x bit of port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss0 . set the pm13x bit of port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. when not using the d/a converter, use av ref1 with its potential the same as that of the v dd0 . pd780058, 780058y subseries anon r 1 c r 2 the input impedance of the buffer amplifier is r 1 . pd780058, 780058y subseries anon r r 1 c the input impedance of the buffer amplifier is r 1 . if r 1 is not connected, the output becomes undefined when reset is low. 281 user's manual u12013ej3v2ud sbi (serial bus interface) use possible none none 2-wire serial i/o uart none use possible (asynchronous serial interface) time-division transfer function chapter 16 serial interface channel 0 ( pd780058 subseries) the pd780058 subseries incorporates three serial interface channels. differences between channels 0, 1, and 2 are as follows (see chapter 18 serial interface channel 1 for details of serial interface channel 1 and chapter 19 serial interface channel 2 for details of serial interface channel 2). table 16-1. differences between channels 0, 1, and 2 serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit serial transfer end interrupt request flag (csiif0) channel 1 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit automatic transmit/ receive function serial transfer end interrupt request flag (csiif1) channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) clock selection transfer method transfer end flag 3-wire serial i/o 282 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.1 functions of serial interface channel 0 serial interface channel 0 employs the following four modes. operation stop mode 3-wire serial i/o mode sbi (serial bus interface) mode 2-wire serial i/o mode caution do not change the operating mode (3-wire serial i/o, 2-wire serial i/o, or sbi) while serial interface channel 0 is enabled to operate. to change the operating mode, stop the serial operation first. (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced in this mode. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for the serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. (3) sbi (serial bus interface) mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using the serial clock (sck0) and serial data bus (sb0 or sb1) lines (see figure 16-1 ). the sbi mode conforms to the nec electronics serial bus format, and transmits or receives three types of transfer data: ?ddresses? ?ommands? and ?ata? ? address: data to select the target device for serial communication ? command: data to give an instruction to the target device ? data: data actually transferred actually, the master device outputs an ?ddress?to the serial bus to select one of the slave devices with which the master device is to communicate. after that, ?ommands?and ?ata?are transmitted or received between the master and slave devices (this is the serial transfer). the receiver can automatically identify the received data as an ?ddress? ?ommand? or ?ata?by hardware. this function enables the i/o ports to be used effectively and the serial interface control portions of the application program to be simplified. in this mode, the wakeup function for handshake and the output function of acknowledge and busy signals can also be used. 283 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (4) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using the two lines of the serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables support of any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in an increased number of available i/o ports. figure 16-1. serial bus interface (sbi) system configuration example master cpu sck0 sb0 sck0 sb0 slave cpu1 sck0 sb0 slave cpu2 sck0 sb0 slave cpun v dd0 284 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.2 configuration of serial interface channel 0 serial interface channel 0 consists of the following hardware. table 16-2. configuration of serial interface channel 0 item configuration registers serial i/o shift register 0 (sio0) slave address register (sva) control registers timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) note note see figure 6-5 block diagram of p20, p21, and p23 to p26 and figure 6-6 block diagram of p22 and p27 . 285 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-2. block diagram of serial interface channel 0 remark the output control block performs selection between cmos output and n-ch open-drain output. csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 controller output control selector si0/sb0/ p25 pm25 output control so0/sb1/ p26 pm26 output control sck0/ p27 pm27 selector p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus bus release/ command/ acknowledge detector serial clock counter serial clock controller clr d set q match busy/ acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector tcl33 tcl32 tcl31 tcl30 4 timer clock select register 3 f xx /2 to f xx /2 8 intcsi0 cld sic svam csim01 csim00 csim01 csim00 slave address register (sva) svam serial bus interface control register serial i/o shift register 0 (sio0) to2 interrupt timing specify register 286 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (1) serial i/o shift register 0 (sio0) sio0 is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/ reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts a serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the sbi mode or 2-wire serial i/o mode, the bus pins must serve for both input and output. thus, in the case of a device for reception, write ffh to sio0 in advance (except when address reception is carried out by setting bit 5 (wup) of csim0 to 1). in the sbi mode, the busy state can be cleared by writing data to sio0. in this case, bit 7 (bsye) of the serial bus interface control register (sbic) is not cleared to 0. reset input makes sio0 undefined. (2) slave address register (sva) sva is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus. the sva is set with an 8-bit memory manipulation instruction. this register is not used in the 3-wire serial i/o mode. the master device outputs a slave address to the connected slave devices for selection of a particular slave device. these two data (the slave address output from the master device and the sva value) are compared by an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address comparison can also be executed on the data of lsb-masked higher 7 bits by setting bit 4 (svam) of the interrupt timing specify register (sint) to 1. if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. in the sbi mode, the wakeup function can be used by setting bit 5 (wup) of csim0 to 1. in this case, the interrupt request signal (intcsi0) is generated only when the slave address output by the master matches with the sva value, and it can be learned by this interrupt request that the master requests communication. if bit 5 (sic) of the interrupt timing specify register (sint) is set to 1, the wakeup function cannot be used even if wup is set to 1 (an interrupt request signal is generated when bus release is detected). to use the wakeup function, clear sic to 0. further, an error can be detected by using sva when the device transmits data as a master or slave device in the sbi or 2-wire serial i/o mode. reset input makes sva undefined. 287 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (3) so0 latch this latch holds the si0/sb0/p25 and so0/sb1/p26 pin levels. it can be directly controlled by software. in the sbi mode, this latch is set upon termination of the 8th serial clock. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. (5) serial clock controller this circuit controls serial clock supply to serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/p27 pin. (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates an interrupt request signal in the following cases. in the 3-wire serial i/o mode and 2-wire serial i/o mode this circuit generates an interrupt request signal every eight serial clocks. in the sbi mode when wup is 0 ........... generates an interrupt request signal every eight serial clocks. when wup is 1 ........... generates an interrupt request signal when the serial i/o shift register 0 (sio0) value matches the slave address register (sva) value after address reception. remark wup is the wakeup function specification bit. it is bit 5 of serial operating mode register 0 (csim0). when using the wakeup function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. (7) busy/acknowledge output circuit and bus release/command/acknowledge detector these two circuits output and detect various control signals in the sbi mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. 288 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.3 control registers of serial interface channel 0 the following four registers are used to control serial interface channel 0. timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) serial bus interface control register (sbic) interrupt timing specification register (sint) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. 289 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-3. format of timer clock select register 3 caution when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs:bit 0 of oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w 290 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (2) serial operating mode register 0 (csim0) this register sets the serial interface channel 0 serial clock, operating mode, operation enable/stop wakeup function and displays the address comparator match signal. csim0 is set with a 1-bit or an 8-bit memory manipulation instruction. reset input clears csim0 to 00h. caution do not change the operating mode (3-wire serial i/o, 2-wire serial i/o, or sbi) while serial interface channel 0 is enabled to operate. to change the operating mode, stop the serial operation first. figure 16-4. format of serial operating mode register 0 (1/2) (cont d) notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos i/o) when used only for transmission. 3. can be used freely as a port function. remark : don t care pm : port mode register p : port output latch sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 0 sck0 (cmos i/o) r/w 1 clock specified by bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos i/o) sb0 (n-ch open-drain i/o) sb1 (n-ch open-drain i/o) p26 (cmos i/o) 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos i/o) 2-wire serial l/o mode 0 sck0 (n-ch open-drain i/o) 1 11 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos i/o) sb0 (n-ch open-drain i/o) sb1 (n-ch open-drain i/o) p26 (cmos i/o) note 2 291 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-4. format of serial operating mode register 0 (2/2) notes 1. when using the wakeup function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. 2. when csie0 = 0, coi becomes 0. wup 0 1 wakeup function control note 1 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w coi 0 1 slave address comparison result flag note 2 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enabled r/w 292 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (3) serial bus interface control register (sbic) this register sets the serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. figure 16-5. format of serial bus interface control register (1/2) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (relt, cmdt, and ackt) are 0 when read after data setting. 2. csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, the so0 iatch is set to 1. after the so0 latch is set, is relt automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld = 1) clear conditions (reld = 0) when bus release signal (rel) is detected when transfer start instruction is executed if sio0 and sva values do not match in address reception when csie0 = 0 when reset input is applied r cmdd command detection clear conditions (cmdd = 0) when transfer start instruction is executed when bus release signal (rel) is detected when csie0 = 0 when reset input is applied set conditions (cmdd = 1) when command signal (cmd) is detected ackt the acknowledge signal is output in synchronization with the falling edge of the sck0 clock just after execution of the instruction that sets this bit to 1, and after acknowledge signal output, ackt is automatically cleared to 0. ackt is used with acke = 0. ackt is also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w 293 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-5. format of serial bus interface control register (2/2) note the busy mode can be cleared by start of serial interface transfer. however, the bsye flag is not cleared to 0. remark csie0: bit 7 of serial operating mode register 0 (csim0) acke acknowledge signal automatic output control 0 acknowledge signal automatic output disable (output by ackt enabled) the acknowledge signal is output in synchronization with the falling edge of the 9th sck0 clock (automatically output when acke = 1). before completion of transfer the acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction that sets this bit to 1 (automatically output when acke = 1). however, acke is not automatically cleared to 0 after acknowledge signal is output. after completion of transfer 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) falling edge of sck0 immediately after busy mode is released after executing the transfer start instruction when csie0 = 0 when reset input is applied set conditions (ackd = 1) when acknowledge signal (ack) is detected at the rising edge of the sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disable the busy signal which is output in synchronization with the falling edge the sck0 clock just after execution of the instruction that clears this bit to 0. r/w note 1 output the busy signal at the falling edge of the sck0 clock following the acknowledge signal. 294 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (4) interrupt timing specification register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0/p27 pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. figure 16-6. format of interrupt timing specification register notes 1. bit 6 (cld) is a read-only bit. 2. when using wakeup function in the sbi mode, clear sic to 0. 3. when csie0 = 0, cld becomes 0. caution be sure to clear bits 0 to 3 to 0. remark sva: slave address register csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6><5><4>3210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt source selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 3 low level high level r/w r/w r 1 295 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.4 operations of serial interface channel 0 the following four operating modes are available for serial interface channel 0. operation stop mode 3-wire serial i/o mode sbi mode 2-wire serial i/o mode 16.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. serial i/o shift register 0 (sio0) does not carry out shift operations either and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0, p26/so0/sb1, and p27/sck0 pins can be used as ordinary i/o ports. (1) register setting the operation stop mode is set by serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 296 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. communication is carried out with the three lines of the serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set by serial operating mode register 0 (csim0) and the serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. 297 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. be sure to clear wup to 0 when the 3-wire serial i/o mode is selected. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 sbi mode (see 16.4.3 sbi mode operation .) r/w 1 clock specified by bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 wup 0 1 wakeup function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register data in sbi mode r/w 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos i/o) 2-wire serial i/o mode (see 16.4.4 2-wire serial i/o mode operation .) 11 note 2 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 csie0 coi wup csim04 csim03 csim02 csim01 csim00 298 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, the so0 iatch is set to 1. after the so0 iatch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w 299 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operations of serial i/o shift register 0 (sio0) are carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 16-7. 3-wire serial i/o mode timing the so0 pin is a cmos output pin and outputs the current so0 latch status. thus, the so0 pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (see 16.4.5 sck0/p27 pin output manipulation ). (3) other signals figure 16-8 shows the relt and cmdt operations. figure 16-8. relt and cmdt operations si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer relt cmdt so0 latch 300 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (4) msb/lsb switching as the start bit in the 3-wire serial i/o mode, it is possible to select transfer to start from the msb or lsb. figure 16-9 shows the configuration of serial i/o shift register 0 (sio0) and the internal bus. as shown in the figure, the msb/lsb can be read or written in reverse form. msb/lsb switching as the start bit can be specified by bit 2 (csim02) of serial operating mode register 0 (csim0). figure 16-9. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to sio0. (5) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface channel 0 operation control bit (csie0) = 1. internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 serial i/o shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch 301 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.4.3 sbi mode operation sbi (serial bus interface) is a high-speed serial interface that complies with the nec electronics serial bus format. sbi uses a single master device and employs a clocked serial i/o format with the addition of a bus configuration function. this function enables devices to communicate using only two lines. thus, when making up a serial bus with two or more microcontrollers and peripheral ics, the number of ports to be used and the number of wires on the board can be decreased. the master device outputs three kinds of data to slave devices on the serial data bus: addresses to select a device to be communicated with, commands to instruct the selected device, and data which is actually required. the slave device can identify the received data as address , command , or data by hardware. an application program that controls serial interface channel 0 can be simplified by using this function. the sbi function is incorporated into various devices including the 75x/xl series and 78k series. figure 16-10 shows a serial bus configuration example when a cpu having a serial interface compliant with sbi and peripheral ics are used. in sbi, the sb0 (sb1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as a wired-or configuration. in addition, a pull-up resistor must be connected to the serial data bus line. when the sbi mode is used, see (11) sbi mode precautions (d) described later. figure 16-10. example of serial bus configuration with sbi caution when exchanging the master cpu/slave cpu, a pull-up resistor is necessary for the serial clock line (sck0) as well because serial clock line (sck0) input/output switching is carried out asynchronously between the master and slave cpus. master cpu sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) slave cpu address 1 slave cpu address 2 slave ic address n serial clock serial data bus v dd0 302 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (1) sbi functions in the conventional serial i/o format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary to provide chip select signals to identify commands and data, and to judge the busy state, because only the data transfer function is available. if these operations are to be controlled by software, the software load becomes very heavy. in sbi, a serial bus can be configured with the two signal lines of the serial clock sck0 and serial data bus sb0 (sb1). thus, use of sbi leads to a reduction in the number of microcontroller ports and the amount of wiring and routing on the board. the sbi functions are described below. (a) address/command/data identification function serial data is distinguished as addresses, commands, and data. (b) chip select function by address transmission the master executes slave chip selection by address transmission. (c) wakeup function the slave can easily judge address reception (chip select judgment) using the wakeup function (which can be set/reset by software). when the wakeup function is set, the interrupt request signal (intcsi0) is generated upon reception of a match address. thus, when communication is executed with two or more devices, the cpu except the selected slave device can operate regardless of serial communications. (d) acknowledge signal (ack) control function the acknowledge signal used to check serial data reception is controlled. (e) busy signal (busy) control function the busy signal used to report the slave busy state is controlled. 303 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (2) sbi definition the sbi serial data format and the signals to be used are defined as follows. serial data to be transferred by sbi consists of three kinds of data: address , command , and data . figure 16-11 shows the address, command, and data transfer timing. figure 16-11. sbi transfer timing remark the broken lines indicate the ready status. the bus release signal and the command signal are output by the master device. busy is output by the slave device. ack can be output by either the master or slave device (normally, the 8-bit data receiver outputs). serial clocks continue to be output by the master device from 8-bit data transfer start to busy reset. sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal address command data 304 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (a) bus release signal (rel) the bus release signal is recognized when the sb0 (sb1) line changes from low level to high level when the sck0 line is at high level (without serial clock output). this signal is output by the master device. figure 16-12. bus release signal the bus release signal indicates that the master device is going to transmit an address to the slave device. the slave device incorporates hardware to detect the bus release signal. caution the transition of the sb0 (sb1) line from low to high when the sck0 line is high is recognized as a bus release signal. if the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release signal. exercise care in wiring so that noise is not superimposed on the signal lines. (b) command signal (cmd) the command signal is recognized when the sb0 (sb1) line changes from high level to low level when the sck0 line is at high level (without serial clock output). this signal is output by the master device. figure 16-13. command signal the command signal indicates that the master is going to transmit a command to the slave (however, a command signal following a bus release signal indicates that an address is transmitted). the slave device incorporates hardware to detect the command signal. caution the transition of the sb0 (sb1) line from high to low when the sck0 line is high is recognized as a command signal. if the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a command signal. exercise care in wiring so that noise is not superimposed on the signal lines. sck0 h sb0 (sb1) sck0 h sb0 (sb1) 305 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (c) address an address is 8-bit data which the master device outputs to the slave devices connected to the bus line in order to select a particular slave device. figure 16-14. addresses 8-bit data following bus release and command signals is defined as an address . in the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. if the 8-bit data matches the slave address, the slave device has been selected. after that, communication with the master device continues until a release instruction is received from the master device. figure 16-15. slave selection by address sck0 a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address command signal bus release signal master slave 1 not selected slave 2 selected slave 3 not selected slave 4 not selected slave 2 address transmission 306 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (d) commands and data the master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. figure 16-16. commands figure 16-17. data 8-bit data following a command signal is defined as command data. 8-bit data without a command signal is defined as data . command and data operation procedures can be determined by the user according to their communication specifications. sck0 d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0 (sb1) data sck0 c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0 (sb1) command command signal 307 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (e) acknowledge signal (ack) the acknowledge signal is used to check serial data reception between the transmitter and receiver. figure 16-18. acknowledge signal [when output in synchronization with 11th sck0 clock] [when output in synchronization with 9th sck0 clock] remark the broken lines indicate the ready status. the acknowledge signal is one-shot pulse generated at the falling edge of sck0 after 8-bit data transfer. it can be positioned anywhere and can be synchronized with any sck0 clock. after 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. if the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. sck0 sb0 (sb1) 8 9 10 11 ack 89 ack sck0 sb0 (sb1) 308 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (f) busy signal (busy) and ready signal (ready) the busy signal is used to report to the master device that the slave device is not ready for data transmission/reception. the ready signal is used to report to the master device that the slave device is ready for data transmission/reception. figure 16-19. busy and ready signals in sbi, the slave device notifies the master device of the busy state by setting the sb0 (sb1) line to low level. busy signal output follows acknowledge signal output from the master or slave device. it is set/reset at the falling edge of sck0. when the busy signal is reset, the master device automatically terminates the output of the sck0 serial clock. when the busy signal is reset and the ready signal is set, the master device can start the next transfer. caution in the sbi mode, the busy signal is output until the next serial clock (sck0) falls after a command that resets the busy signal has been issued. if wup is set to 1 during this period by mistake, the busy signal is not reset. therefore, be sure to confirm that the sb0 (sb1) pin has gone high after resetting the busy signal, by setting wup to 1. ready ack sck0 sb0 (sb1) busy 89 309 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (3) register setting the sbi mode is set by serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specification register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as a port function. 3. when using the wakeup function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. 4. when csie0 = 0, coi becomes 0. remark : don t care pm : port mode register p : port output latch sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos i/o) sb0 (n-ch open-drain i/o) sb1 (n-ch open-drain i/o) p26 (cmos i/o) wup 0 1 wakeup function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w 11 3-wire serial i/o mode (see 16.4.2 3-wire serial i/o mode operation .) 2-wire serial i/o mode (see 16.4.4 2-wire serial i/o mode operation .) coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 sck0 (cmos i/o) 310 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (relt, cmdt, and ackt) are 0 when read after data setting. 2. csie0: bit 7 of serial operating mode register 0 (csim0) (cont d) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, the so0 iatch is set to 1. after the so0 latch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld = 1) clear conditions (reld = 0) when bus release signal (rel) is detected when transfer start instruction is executed if sio0 and sva values do not match in address reception (only when wup = 1) when csie0 = 0 when reset input is applied r cmdd command detection clear conditions (cmdd = 0) when transfer start instruction is executed when bus release signal (rel) is detected when csie0 = 0 when reset input is applied set conditions (cmdd = 1) when command signal (cmd) is detected the acknowledge signal is output in synchronization with the falling edge of the sck0 clock just after execution of the instruction that sets this bit to 1 and, after acknowledge signal output, ackt is automatically cleared to 0. ackt is used with acke = 0. ackt is also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w acke acknowledge signal automatic output control 0 acknowledge signal automatic output disable (output by ackt enabled) the acknowledge signal is output in synchronization with the falling edge of the 9th sck0 clock (automatically output when acke = 1). before completion of transfer the acknowledge signal is output in synchronization with falling edge of the sck0 clock just after execution of the instruction that sets this bit to 1 (automatically output when acke = 1). however, acke is not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w ackt 311 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud note busy mode can be cleared by start of serial interface transfer. however, the bsye flag is not cleared to 0. remark csie0: bit 7 of serial operating mode register 0 (csim0) r ackd acknowledge detection clear conditions (ackd = 0) when sck0 falls immediately after busy mode is released after transfer start instruction execution. when csie0 = 0 when reset input is applied set conditions (ackd = 1) when the acknowledge signal (ack) is detected at the rising edge of the sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disable the busy signal which is output in synchronization with the falling edge of sck0 clock just after execution of the instruction that clears this bit to 0 (set ready status). r/w note 1 output the busy signal at the falling edge of the sck0 clock following the acknowledge signal. 312 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (c) interrupt timing specification register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. caution be sure to clear bits 0 to 3 to 0. notes 1. bit 6 (cld) is a read-only bit. 2. when using wakeup function in the sbi mode, clear sic to 0. 3. when csie0 = 0, cld becomes 0. remark sva: slave address register csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6><5><4>3210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt source selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 3 low level high level r/w r/w r 1 313 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (4) various signals figures 16-20 to 16-25 show various signals and flag operations in sbi. table 16-3 lists various signals in sbi. figure 16-20. relt, cmdt, reld, and cmdd operations (master) figure 16-21. reld and cmdd operations (slave) sck0 sb0 (sb1) relt cmdt cmdd reld sio0 slave address write to sio0 (transfer start instruction) write ffh to sio0 (transfer start instruction) sio0 sck0 sb0 (sb1) reld cmdd transfer start instruction a7 a6 a1 a0 12 789 ready a7 a6 a1 a0 ack slave address when addresses match when addresses do not match 314 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-22. ackt operation caution do not set ackt before completion of transfer. sck0 6 sb0 (sb1) ackt 7 8 9 d2 d1 d0 ack if ackt is set during this period ack signal is output for a period of one clock just after setting 315 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-23. acke operations (a) when acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when acke = 0 upon completion of transfer (d) when acke = 1 period is short sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 ack when acke = 1 at this point ack signal is output at 9th clock sck0 sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 when acke = 0 at this point ack signal is not output sck0 sb0 (sb1) acke 7 89 d1 d0 ack 6 d2 if acke is set during this period and it is still 1 at the fallin g ed g e of the next sck0 ack signal is output for a period of one clock just after setting sck0 sb0 (sb1) acke if acke is set and then cleared during this period and it is still 0 at the falling edge of sck0 ack signal is not output d2 d1 d0 sck0 316 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-24. ackd operations (a) when ack signal is output at 9th sck0 clock (b) when ack signal is output after 9th sck0 clock (c) clear timing when transfer start is instructed during busy figure 16-25. bsye operation sck0 sb0 (sb1) ackd 789 d1 d0 ack 6 d2 transfer start instruction sio0 transfer start sb0 (sb1) ackd ack 9 sio0 78 d1 6 d2 d0 transfer start instruction transfer start sck0 sck0 sb0 (sb1) bsye 7 89 ack 6 when bsye = 1 at this point busy if bsye is reset during this period and it is still 0 at the falling edge of sck0 d2 d1 d0 sck0 sb0 (sb1) ackd ack 9 transfer start instruction sio0 78 d1 6 d2 d0 d6 d7 busy 317 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud table 16-3. various signals in sbi mode (1/2) timing chart definition signal name output device output conditions effects on flag meaning of signal cmd signal is output to indicate that transmit data is an address. i) transmit data is an address after rel signal output. ii) rel signal is not output and trans- mit data is an command. low-level signal output to sb0 (sb1) during one- clock period of sck0 after completion of serial reception [synchronous busy signal] low-level signal output to sb0 (sb1) following acknowledge signal 1 bsye = 0 2 execution of instruction for data write to sio0 (transfer start instruction) master/ slave sb0 (sb1) rising edge when sck0 = 1 master bus release signal (rel) relt set reld set cmdd clear cmdd set cmdt set master command signal (cmd) sb0 (sb1) falling edge when sck0 = 1 acknowledge signal (ack) 1 acke = 1 2 ackt set ackd set completion of reception slave busy signal (busy) bsye = 1 serial receive disabled because of processing serial receive enabled slave ready signal (ready) high-level signal output to sb0 (sb1) before serial transfer start and after completion of serial transfer [synchronous busy output] sck0 d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9 sck0 h sb0 (sb1) h sb0 (sb1) sck0 318 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud timing chart definition signal name output device output conditions effects on flag meaning of signal synchronous clock to output address/command/data, ack signal, synchronous busy signal, etc. address/ command/data is transferred with the first eight synchronous clocks. 8-bit data transferred in synchronization with sck0 after output of only cmd signal without rel signal output master numeric values to be processed by slave or master device serial clock (sck0) timing of signal output to serial data bus address value of slave device on the serial bus address (a7 to a0) 8-bit data transferred in synchronization with sck0 after output of rel and cmd signals master command (c7 to c0) instructions and messages to the slave device master/ slave data (d7 to d0) 8-bit data transferred in synchronization with sck0 without output of rel and cmd signals table 16-3. various signals in sbi mode (2/2) when csie0 = 1, execution of instruction for data write to sio0 (serial transfer start instruction) note 2 notes 1. when wup = 0, csiif0 is set at the rising edge of the 9th clock of sck0. when wup = 1, an address is received. only when the address matches the slave address register (sva) value, csiif0 is set (if the address does not match the value of sva, reld is cleared). 2. in the busy state, transfer starts after the ready state is set. master csiif0 set (rising edge of 9th clock of sck0) note 1 sck0 sb0 (sb1) 1278910 sck0 sb0 (sb1) 1278 rel cmd sck0 sb0 (sb1) 1278 cmd sck0 sb0 (sb1) 1278 319 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (5) pin configuration the serial clock pin sck0 and serial data bus pin sb0 (sb1) have the following configurations. (a) sck0 ............ serial clock i/o pin 1 master ... cmos and push-pull output 2 slave ...... schmitt input (b) sb0 (sb1) .... serial data i/o alternate-function pin both master and slave devices have an n-ch open-drain output and a schmitt input. because the serial data bus line has an n-ch open-drain output, an external pull-up resistor is necessary. figure 16-26. pin configuration caution because the n-ch open-drain output must made to go into a high-impedance state during data reception, write ffh to serial i/o shift register 0 (sio0) in advance. the n-ch open-drain output can always go into a high-impedance state during transfer. however, when the wake- up function specification bit (wup) = 1, the n-ch open-drain output always goes into a high- impedance state. thus, it is not necessary to write ffh to sio0 before reception. si0 so0 si0 so0 (clock input) clock output master service clock input (clock output) serial clock sck0 sck0 r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open-drain n-ch open-drain slave device v dd0 v ss0 v ss0 320 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (6) address match detection method in the sbi mode, the master transmits a slave address to select a specific slave device. a match of the addresses can be automatically detected by hardware. csiif0 is set only when the slave address transmitted by the master matches the address set to sva when the wakeup function specification bit (wup) = 1. if bit 5 (sic) of the interrupt timing specify register (sint) is set, the wakeup function cannot be used even if wup is set (an interrupt request signal is generated when bus release is detected). to use the wake-up function, clear sic to 0. cautions 1. slave selection/non-selection is detected by matching of the slave address received after bus release (reld = 1). for this match detection, the match interrupt request (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. 2. when detecting selection/non-selection without the use of an interrupt request with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) error detection in the sbi mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, serial i/o shift register 0 (sio0). thus, transmit errors can be detected in the following ways. (a) method of comparing sio0 data before and after transmission in this case, if the two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, the coi bit (match signal coming from the address comparator) of serial operating mode register 0 (csim0) is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. (8) communication operation in the sbi mode, the master device normally selects one slave device as the communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave device. figures 16-27 to 16-30 show data communication timing charts. shift operations of serial i/o shift register 0 (sio0) are carried out at the falling edge of the serial clock (sck0). transmit data is latched into the so0 latch and is output with the msb set as the first bit from the sb0/p25 or sb1/p26 pin. receive data input to the sb0 (or sb1) pin at the rising edge of sck0 is latched into sio0. 321 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-27. address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 sck0 pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation wup 0 ackt set program processing cmdd set intcsi0 generation ack output hardware operation cmdt set relt set cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd clear cmdd set reld set serial reception busy output ready (when sva = sio0) address busy clear busy clear 322 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-28. command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd set serial reception busy output ready command busy clear busy clear sio0 read command analysis 323 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-29. data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) serial reception busy output ready data busy clear busy clear sio0 read 324 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud figure 16-30. data transmission from slave device to master device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial reception intcsi0 generation ack output serial reception hardware operation program processing intcsi0 generation ackd set hardware operation ffh write to sio0 master device processing (receiver) transfer line slave device processing (transmitter) serial transmission busy output ready data busy clear write to sio0 sck0 stop busy clear 12 ready busy d7 d6 ackt set sio0 read receive data processing ffh write to sio0 write to sio0 325 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (9) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface channel 0 operation control bit (csie0) = 1 internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to ??after data write to sio0, transfer does not start. 2. because the n-ch open-drain output must go into a high-impedance state during data reception, write ffh to sio0 in advance. however, when the wakeup function specification bit (wup) = 1, the n-ch open-drain output always goes into a high-impedance state. thus, it is not necessary to write ffh to sio0 before reception. 3. if data is written to sio0 when the slave is busy, the data is not lost. when the busy state is cleared and sb0 (or sb1) input is set to the high level (ready) state, transfer starts. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. for pins that are to be used for data i/o, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set the p25 and p26 output latches to 1. <2> set bit 0 (relt) of the serial bus interface control register (sbic) to 1. <3> reset the p25 and p26 output latches from 1 to 0. (10) judging busy state of slave when the device is in the master mode, follow the procedure below to judge whether the slave device is in the busy state or not. <1> detect acknowledge signal (ack) or interrupt request signal generation. <2> set the port mode register pm25 (or pm26) of the sb0/p25 (or sb1/p26) pin to the input mode. <3> read out the pin state (when the pin level is high, the ready state is set). after detection of the ready state, clear the port mode register to 0 and return to the output mode. 326 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (11) sbi mode precautions (a) slave selection/non-selection is detected by match detection of the slave address received after bus release (reld = 1). for this match detection, the match interrupt request (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. (b) when detecting selection/non-selection without the use of an interrupt with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) in the sbi mode, the busy signal is output until the next serial clock falls after a command that resets the busy signal has been issued. if wup is set to 1 during this period by mistake, the busy signal is not reset. therefore, be sure to confirm that the sb0 (sb1) pin has gone high after resetting the busy signal, by setting wup to 1. (d) for pins that are to be used for data i/o, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set the p25 and p26 output latches to 1. <2> set bit 0 (relt) of the serial bus interface control register (sbic) to 1. <3> reset the p25 and p26 output latches from 1 to 0. (e) the transition of the sb0 (sb1) line from low to high or from high to low when the sck0 line is high is recognized as a bus release signal or a command signal, respectively. if the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release signal (or a command signal). exercise care in wiring so that noise is not superimposed on the signal lines. 327 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.4.4 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with the two lines of the serial clock (sck0) and serial data input/output (sb0 or sb1). figure 16-31. serial bus configuration example using 2-wire serial i/o mode (1) register setting the 2-wire serial i/o mode is set by serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specification register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd0 v dd0 328 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as a port function. 3. be sure to set wup to 0 in the 2-wire serial i/o mode. 4. when csie0 = 0, coi becomes 0. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 wup 0 1 wakeup function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w 2-wire serial l/o mode 0 1 11 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos i/o) sb0 (n-ch open-drain i/o) sb1 (n-ch open-drain i/o) p26 (cmos i/o) 3-wire serial i/o mode (see 16.4.2 3-wire serial i/o mode operation ) sbi mode (see 16.4.3 sbi mode operation ) coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 sck0 (n-ch open-drain i/o) 329 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. csie0: bit 7 of serial operating mode register 0 (csim0) (c) interrupt timing specification register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. caution be sure to clear bits 0 to 3 to 0. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. remark csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, the so0 iatch is set to 1. after the so0 iatch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w <6><5><4>3210 7 symbol sint 0 cld sic 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w sic 0 intcsi0 interrupt factor selection csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 2 low level high level r/w r 1 svam 330 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operations of serial i/o shift register 0 (sio0) are carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/p25 (or sb1/ p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the sio0 at the rising edge of sck0. upon termination of 8-bit transfer, the sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 16-32. 2-wire serial i/o mode timing the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain i/o and thus it must be externally connected to a pull-up resistor. because an n-ch open-drain output must go into a high-impedance state during data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (see 16.4.5 sck0/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the falling edge of sck0 end of transfer 331 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud (3) other signals figure 16-33 shows the relt and cmdt operations. figure 16-33. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface channel 0 operation control bit (csie0) = 1 internal serial clock is stopped or sck0 is high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch open-drain output must go into a high-impedance state during data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, serial i/o shift register 0 (sio0). thus, transmit errors can be detected in the following ways. (a) method of comparing sio0 data before and after transmission in this case, if the two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, the coi bit (match signal coming from the address comparator) of serial operating mode register 0 (csim0) is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. relt cmdt so0 latch 332 chapter 16 serial interface channel 0 ( pd780058 subseries) user's manual u12013ej3v2ud 16.4.5 sck0/p27 pin output manipulation because the sck0/p27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. p27 output latch manipulation enables any value of sck0 to be set by software. (the si0/sb0 and so0/sb1 pins are controlled by bits 0 and 1 (relt and cmdt) of the serial bus interface control register (sbic).) the procedure for manipulating the sck0/p27 pin output is described below. 1 set serial operating mode register 0 (csim0) (sck0 pin: output mode, serial operation: enabled). sck0 = 1 while serial transfer is suspended. 2 manipulate the p27 output latch with a bit manipulation instruction. figure 16-34. sck0/p27 pin configuration to internal circuit sck0/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0, or 1 and 1. sck0 (1 while transfer is stopped) from serial clock controller manipulated by bit manipulation instruction 333 user's manual u12013ej3v2ud 2-wire serial i/o i 2 c bus (inter ic bus) uart use possible (asynchronous serial interface) timer-division transfer function chapter 17 serial interface channel 0 ( pd780058y subseries) the pd780058y subseries incorporates three serial interface channels. differences between channels 0, 1, and 2 are as follows (see chapter 18 serial interface channel 1 for details of serial interface channel 1 and chapter 19 serial interface channel 2 for details of serial interface channel 2). table 17-1. differences between channels 0, 1, and 2 serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit serial transfer end interrupt request flag (csiif0) channel 1 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit automatic transmit/ receive function serial transfer end interrupt request flag (csiif1) channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) clock selection transfer method transfer end flag use possible none none none 3-wire serial i/o 334 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.1 functions of serial interface channel 0 serial interface channel 0 employs the following four modes. operation stop mode 3-wire serial i/o mode 2-wire serial i/o mode ? 2 c (inter ic) bus mode caution do not change the operating mode (3-wire serial i/o, 2-wire serial i/o, or sbi) while serial interface channel 0 is enabled to operate. to change the operating mode, stop the serial operation first. (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced in this mode. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for the serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. (3) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables to cope with any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available i/o ports. 335 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (4) i 2 c (inter ic) bus mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using the two lines of the serial clock (scl) and serial data bus (sda0 or sda1). this mode complies with the i 2 c bus format. in this mode, the transmitter outputs three kinds of data onto the serial data bus: ?tart condition? ?ata? and ?top condition? to be actually sent or received. the receiver automatically distinguishes the received data as ?tart condition? ?ata? or ?top condition? by hardware. figure 17-1. serial bus configuration example using i 2 c bus master cpu scl sda0 (sda1) scl sda0 (sda1) slave cpu1 slave cpu2 slave cpun v dd0 v dd0 scl sda0 (sda1) scl sda0 (sda1) 336 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.2 configuration of serial interface channel 0 serial interface channel 0 consists of the following hardware. table 17-2. configuration of serial interface channel 0 item configuration registers serial i/o shift register 0 (sio0) slave address register (sva) control registers timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) note note see figure 6-7 block diagram of p20, p21, and p23 to p26 and figure 6-8 block diagram of p22 and p27 . 337 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-2. block diagram of serial interface channel 0 remark the output control block performs selection between cmos output and n-ch open-drain output. csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 controller output control selector si0/sb0/ sda0/p25 pm25 output control so0/sb1/ sda1/p26 pm26 output control sck0/ scl/p27 pm27 selector p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus stop condition/ start condition/ acknowledge detector serial clock counter serial clock controller clr d set q match acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector tcl33 tcl32 tcl31 tcl30 4 timer clock select register 3 f xx /2 to f xx /2 8 intcsi0 cld sic svam bsye clc wrel wat1 wat0 csim01 csim00 to2 1/16 divider csim01 csim00 interrupt timing specify register slave address register (sva) svam serial bus interface control register 2 serial i/o shift register 0 (sio0) 338 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (1) serial i/o shift register 0 (sio0) sio0 is an 8-bit register used to carry out parallel-serial conversion and to carry out serial transmission/ reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts a serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the i 2 c bus mode or 2-wire serial i/o mode, the bus pins must serve for both input and output. therefore, the transmission n-ch transistor of the device which will start reception of data must be turned off beforehand. consequently, write ffh to sio0 in advance. in the i 2 c bus mode, set sio0 to ffh with bit 7 (bsye) of the serial bus interface control register (sbic) set to 1. reset input makes sio0 undefined. caution do not execute an instruction that writes sio0 in the i 2 c bus mode while wup (bit 5 of serial operating mode register 0 (csim0)) = 1. even if such an instruction is not executed, data can be received when the wake-up function is used (wup = 1). for the detail of the wake- up function, see 17.4.4 (1) (c) wake-up function. (2) slave address register (sva) sva is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus. sva is set with an 8-bit memory manipulation instruction. this register is not used in the 3-wire serial i/o mode. the master device outputs a slave address to the connected slave devices for selection of a particular slave device. these two data (the slave address output from the master device and the sva value) are compared with an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address comparison can also be executed on the data of lsb-masked higher 7 bits by setting bit 4 (svam) of the interrupt timing specify register (sint) to 1. if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. in the i 2 c bus mode, the wakeup function can be used by setting bit 5 (wup) of csim0 to 1. in this case, the interrupt request signal (intcsi0) is generated when the slave address output by the master matches the sva value (the interrupt request signal is also generated when the stop condition is detected), and it can be learned by this interrupt request that the master requests for communication. to use the wakeup function, set sic to 1. further, an error can be detected by using sva when the device transmits data as a master or slave device in i 2 c bus mode or 2-wire serial i/o mode. reset input makes sva undefined. (3) so0 latch this latch holds the si0/sb0/sda0/p25 and so0/sb1/sda1/p26 pin levels. it can be directly controlled by software. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. 339 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (5) serial clock controller this circuit controls serial clock supply to serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/scl/p27 pin. (6) interrupt signal generator this circuit controls interrupt request signal generation. it generates interrupt request signals according to the settings of interrupt timing specification register (sint) bits 0 and 1 (wat0, wat1) and serial operation mode register 0 (csim0) bit 5 (wup), as shown in table 17-3. (7) acknowledge output circuit and stop condition/start condition/acknowledge detector these two circuits output and detect various control signals in the i 2 c mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. table 17-3. interrupt request signal generation of serial interface channel 0 serial transfer mode bsye wup wat1 wat0 acke description 3-wire or 2-wire serial i/o mode 0 0 0 0 0 an interrupt request signal is generated each time 8 serial clocks are counted. other than above setting prohibited i 2 c bus mode (transmit) 0 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). normally, during transmission the settings wat21, wat0 = 1, 0, are not used. they are used only when wanting to coordinate receive time and processing systematically using software. ack information is generated by the receiving side, thus acke should be set to 0 (disable). 1 1 0 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ack information is generated by the receiving side, thus acke should be set to 0 (disable). other than above setting prohibited i 2 c bus mode (receive) 1 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ack information is output by manipulating ackt by software after an interrupt request is generated. 1 1 0/1 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). to automatically generate ack information, preset acke to 1 before transfer start. however, in the case of the master, set acke to 0 (disable) before receiving the last data. 1 1 1 1 1 after an address is received, if the values of serial i/ o shift register 0 (si00) and the slave address register (sva) match, and if the stop condition is detected, an interrupt request signal is generated. to automatically generate ack information, preset acke to 1 (enable) before transfer start. other than above setting prohibited remark bsye: bit 7 of the serial bus interface control register (sbic) acke: bit 5 of the serial bus interface control register (sbic) 340 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.3 control registers of serial interface channel 0 the following four registers are used to control serial interface channel 0. timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) serial bus interface control register (sbic) interrupt timing specification register (sint) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. 341 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-3. format of timer clock select register 3 caution when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 10 f xx /2 11 f xx /2 12 mcs = 1 setting prohibited f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) other than above setting prohibited serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w mcs = 0 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) f x /2 13 (0.61 khz) f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) serial clock in i 2 c bus mode serial clock in 2-wire or 3-wire serial i/o mode 342 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (2) serial operating mode register 0 (csim0) this register sets the serial interface channel 0 serial clock, operating mode, operation enable/stop wakeup function and displays the address comparator match signal. csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. caution do not change the operating mode (3-wire serial i/o, 2-wire serial i/o, or sbi) while serial interface channel 0 is enabled to operate. to change the operating mode, stop the serial operation first. figure 17-4. format of serial operating mode register 0 notes 1. bit 6 (coi) is a read-only bit. 2. in i 2 c bus mode, the clock frequency becomes 1/16 of that output from to2. 3. can be used as p25 (cmos input/output) when used only for transmission. 4. can be used freely as a port function. 5. to use the wakeup function (wup = 1), set bit 5 (sic) of the interrupt timing specification register (sint) to 1. do not execute an instruction that writes serial i/o shift register 0 (sio0) while wup = 1. 6. when csie0 = 0, coi becomes 0. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0/scl pin from off-chip 8-bit timer register 2 (tm2) output 0 r/w 1 clock specified by bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0/ p25 pin function so0/sb1/sda1/ p26 pin function sck0/scl/p27 pin function 1 msb lsb 1 0001 note 3 3-wire serial l/o mode si0 note 3 (input) so0 (cmos output) sck0 (cmos i/o) 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain i/o) 1 11 0 0 0 0 0 0 1 1 note 4 note 4 note 4 note 4 msb p25 (cmos i/o) sb0/sda0 (n-ch open-drain sb1/sda1 (n-ch open-drain i/o) p26 (cmos i/o) note 3 wup 0 1 wake-up function control note 5 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w coi 0 1 slave address comparison result flag note 6 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enabled r/w note 2 343 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (3) serial bus interface control register (sbic) this register sets the serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. figure 17-5. format of serial bus interface control register (1/2) note bits 2, 3, and 6 (reld, cmdd, and ackd) are read-only bits. remark csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for stop condition signal output. when relt = 1, the so0 iatch is set to 1. after the so0 latch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for start condition signal output. when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w r reld stop condition detection set conditions (reld = 1) clear conditions (reld = 0) when stop condition signal is detected when transfer start instruction is executed if sio0 and sva values do not match in address reception when csie0 = 0 when reset input is applied r cmdd start condition detection clear conditions (cmdd = 0) when transfer start instruction is executed when stop condition signal is detected when csie0 = 0 when reset input is applied set conditions (cmdd = 1) when start condition signal is detected ackt used to generate the ack signal by software when 8-clock wait mode is selected. keeps sda0 (sda1) low from set instruction (ackt = 1) execution to the next falling edge of scl. ackt is also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w 344 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-5. format of serial bus interface control register (2/2) notes 1. setting should be performed before transfer. 2. if 8-clock wait mode is selected, the acknowledge signal at reception must be output using ackt. 3. the busy mode can be cleared by start of serial interface transfer or reception of address signal. however, the bsye flag is not cleared to 0. 4. when using the wakeup function, be sure to set bsye to 1. remark csie0: bit 7 of serial operating mode register 0 (csim0) acke acknowledge signal output control note 1 0 acknowledge signal automatic output disable (however, output by ackt enabled) used for reception when 8-clock wait mode is selected or for transmission. note 2 enables acknowledge signal automatic output. outputs the acknowledge signal in synchronization with the falling edge of the 9th scl clock cycle (automatically output when acke = 1). however, acke is not automatically cleared to 0 after acknowledge signal is output. used in reception with 9-clock wait mode selected. 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) while executing the transfer start instruction when csie0 = 0 when reset input is applied set conditions (ackd = 1) when acknowledge signal (ack) is detected at the rising edge of the scl clock after completion of transfer bsye control of n-ch open-drain output for transmission in i 2 c bus mode note 4 0 output enabled (transmission) r/w note 3 1 output disabled (reception) 345 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (4) interrupt timing specification register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0/scl pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. figure 17-6. format of interrupt timing specification register (1/2) notes 1. bit 6 (cld) is a read-only bit. 2. when not using the i 2 c mode, clear clc to 0. used in i 2 c bus mode. make scl pin enter high-impedance state unless serial transfer is being performed (except for clock line which is kept high). used to enable master device to generate start condition and stop condition signals. <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic svam clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w wrel 0 wait state has been released. release wait state. automatically cleared to 0 when the state is released (used to cancel wait state by means of wat0 and wat1.) clc 0 1 clock level control note 2 used in i 2 c bus mode. make output level of scl pin low unless serial transfer is being performed. r/w 1 wait sate release control r/w wat1 0 1 wait and interrupt control generates interrupt servicing request at rising edge of 8th sck0 clock cycle (keeping clock output in high impedance). r/w wat0 0 0 used in i 2 c bus mode (8-clock wait). generates interrupt servicing request at rising edge of 8th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 8 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 8 clock pulses are input.) 1 1 used in i 2 c bus mode (9-clock wait). generates interrupt servicing request at rising edge of 9th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 9 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 9 clock pulses are input.) 0 setting prohibited 1 346 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-6. format of interrupt timing specification register (2/2) notes 1. when using the wakeup function in the i 2 c mode, clear sic to 0. 2. when csie0 = 0, cld becomes 0. remark sva: slave address register csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt source selection note 1 csiif0 is set to 1 upon termination of serial interface channel 0 transfer csiif0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer cld 0 1 sck0/scl pin level note 2 low level high level r/w r/w r 1 347 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4 operations of serial interface channel 0 the following four operating modes are available for serial interface channel 0. operation stop mode 3-wire serial i/o mode 2-wire serial i/o mode i 2 c (inter ic) bus mode 17.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. serial i/o shift register 0 (sio0) does not carry out shift operations either and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0/sda0, p26/so0/sb1/sda1, and p27/sck0/scl pins can be used as general i/o ports. (1) register setting the operation stop mode is set by serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 348 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. communication is carried out with the three lines of the serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set by serial operating mode register 0 (csim0) and the serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. be sure to clear wup to 0 when the 3-wire serial i/o mode is selected. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 2-wire serial i/o mode (see 17.4.3 2-wire serial i/o mode operation .) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function 11 wup 0 1 wake-up function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos i/o) i 2 c bus mode (see 17.4.4 i 2 c bus mode operation .) note 2 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 or 349 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, the so0 iatch is set to 1. after the so0 iatch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w 350 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operations of serial i/o shift register 0 (sio0) are carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 17-7. 3-wire serial i/o mode timing the so0 pin is a cmos output pin and outputs the current so0 latch status. thus, the so0 pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (see 17.4.8 sck0/scl/p27 pin output manipulation ). (3) other signals figure 17-8 shows relt and cmdt operations. figure 17-8. relt and cmdt operations si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer relt cmdt so0 latch 351 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (4) msb/lsb switching as the start bit in the 3-wire serial i/o mode, it is possible to select transfer to start from the msb or lsb. figure 17-9 shows the configuration of serial i/o shift register 0 (sio0) and the internal bus. as shown in the figure, the msb/lsb can be read or written in reverse form. msb/lsb switching as the start bit can be specified by bit 2 (csim02) of serial operating mode register 0 (csim0). figure 17-9. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to sio0. (5) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface channel 0 operation control bit (csie0) = 1. internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 serial i/o shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch 352 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4.3 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with the two lines of the serial clock (sck0) and serial data input/output (sb0 or sb1). figure 17-10. serial bus configuration example using 2-wire serial i/o mode (1) register setting the 2-wire serial i/o mode is set by serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd0 v dd0 353 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as port function. 3. be sure to clear wup to 0 when the 2-wire serial i/o mode. 4. when csie0 = 0, coi becomes 0. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified by bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function wup 0 1 wakeup function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain i/o) 1 11 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos i/o) sb0/sda0 (n-ch open-drain i/o) sb1/sda1 (n-ch open-drain i/o p26 (cmos i/o) 3-wire serial i/o mode (see 17.4.2 3-wire serial i/o mode operation ) coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 354 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. csie0: bit 7 of serial operating mode register 0 (csim0) (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. caution be sure to clear bits 0 to 3 to 0 in the 2-wire serial i/o mode is used. remark csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, the so0 iatch is set to 1. after the so0 iatch is set, relt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, the so0 iatch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w svam sic 0 intcsi0 interrupt source selection csiif0 is set to 1 upon termination of serial interface channel 0 transfer csiif0 is set to 1 upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 2 low level high level r/w r 1 355 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operations of serial i/o shift register 0 (sio0) are carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/sda0/p25 (or sb1/sda1/p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the sio0 at the rising edge of sck0. upon termination of 8-bit transfer, the sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 17-11. 2-wire serial i/o mode timing the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. because n-ch open-drain output must go into a high-impedance state during data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (see 17.4.8 sck0/scl/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the falling edge of sck0 end of transfer 356 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (3) other signals figure 17-12 shows the relt and cmdt operations. figure 17-12. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 0 (sio0) when the following two conditions are satisfied. serial interface channel 0 operation control bit (csie0) = 1 internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch open-drain output must go into a high-impedance state during data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, serial i/o shift register 0 (sio0). thus, transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of serial operating mode register 0 (csim0) is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. relt cmdt so0 latch 357 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4.4 i 2 c bus mode operation the i 2 c bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. this mode configures a serial bus that includes only a single master device, and is based on the clocked serial i/o format with the addition of bus configuration functions, which allow the master device to communicate with a number of (slave) devices using only two lines: a serial clock (scl) line and serial data bus (sda0 or sda1) line. consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. in the i 2 c bus specification, the master sends start condition, data, and stop condition signals to slave devices via the serial data bus, while slave devices automatically detect and distinguish the type of signals using a signal detection function incorporated as hardware. the application program that controls the i 2 c bus can be simplified by using this function. an example of a serial bus configuration is shown in figure 17-13. this system below is composed of cpus and peripheral ics having serial interface hardware that complies with the i 2 c bus specification. note that pull-up resistors are required to connect to both the serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. the signals used in the i 2 c bus mode are described in table 17-4. figure 17-13. example of serial bus configuration using i 2 c bus scl sda0 (sda1) scl sda0 (sda1) scl sda0 (sda1) scl sda slave ic slave cpu2 slave cpu1 master cpu v dd0 serial clock serial data bus v dd0 358 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (1) i 2 c bus mode functions in the i 2 c bus mode, the following functions are available. (a) automatic identification of serial data slave devices automatically detect and identify start condition, data, and stop condition signals sent in series via the serial data bus. (b) chip selection by specifying device addresses the master device can select a specific slave device connected to the i 2 c bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) wakeup function when address data is sent from the master device, slave devices compare it with the value registered in their internal slave address registers. if the values in one of the slave devices match, the slave device internally generates an interrupt request signal to terminate the current processing and communicates with the master device (the interrupt request also occurs when the stop condition is detected). therefore, cpus other than the selected slave device on the i 2 c bus can perform independent operations during the serial communication. (d) acknowledge signal (ack) control function the master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) wait signal (wait) control function when a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) i 2 c bus definition this section describes the format of serial data communications and functions of the signals used in the i 2 c bus mode. first, the transfer timing of the ?tart condition? ?ata? and ?top condition?signals, which are output onto the signal data bus of the i 2 c bus, is shown in figure 17-14. figure 17-14. i 2 c bus serial data transfer timing the start condition, slave address, and stop condition signals are output by the master. the acknowledge signal (ack) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). a serial clock (scl) is continuously supplied from the master device. 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 address r/w ack data ack data ack scl start condition sda0 (sda1) stop condition 359 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (a) start condition when the sda0 (sda1) pin level is changed from high to low while the scl pin is high, this transition is recognized as the start condition signal. this start condition signal, which is created using the scl and sda0 (or sda1) pins, is output from the master device to slave devices to initiate a serial transfer. see 17.4.5 cautions on use of i 2 c bus mode , for details of the start condition output. the start condition signal is detected by hardware incorporated in slave devices. figure 17-15. start condition (b) address the 7 bits following the start condition signal are defined as an address. the 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. each slave device on the bus line must therefore have a different address. therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (sva). after the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. figure 17-16. address (c) transfer direction specification the 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. if this bit is 0, it is the master device which will send data to the slave. if it is 1, it is the slave device which will send data to the master. figure 17-17. transfer direction specification h scl sda0 (sda1) 1234567 a6 a5 a4 a3 a2 a1 a0 r/w address scl sda0 (sda1) 234567 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification scl 8 1 sda0 (sda1) 360 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (d) acknowledge signal (ack) the acknowledge signal indicates that the transferred serial data has definitely been received. this signal is used between the transmitting side and receiving side devices for confirmation of correct data transfer. in principle, the receiving side device returns an acknowledge signal to the transmitting device each time it receives 8-bit data. the only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. the transmitting side that has transferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. if the transmitting side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. if this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. figure 17-18. acknowledge signal (e) stop condition if the sda0 (sda1) pin level changes from low to high while the scl pin is high, this transition is defined as a stop condition signal. the stop condition signal is output from the master to the slave device to terminate a serial transfer. the stop condition signal is detected by hardware incorporated in the slave device. figure 17-19. stop condition 1234567 a6 a5 a4 a3 a2 a1 a0 r/w scl sda0 (sda1) 9 8 ack h scl sda0 (sda1) 361 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (f) wait signal (wait) the wait signal is output by a slave device to inform the master device that the slave device is in a wait state due to preparing for transmitting or receiving data. during the wait state, the slave device continues to output the wait signal by keeping the scl pin low to delay subsequent transfers. when the wait state is released, the master device can start the next transfer. for the releasing operation of slave devices, see 17.4.5 cautions on use of i 2 c bus mode . figure 17-20. wait signal (a) wait of 8 clock cycles (b) wait of 9 clock cycles scl of master device d2 d1 d0 ack d7 output by manipulating ackt 6789 1 3 24 d6 d5 d4 set low because slave device drives low, though master device returns to hi-z state. no wait is inserted after 9th clock cycle (and before master device starts next transfer). scl of slave device scl sda0 (sda1) scl of master device set low because slave device drives low, though master device returns to hi-z state. scl of slave device scl d2 d1 d0 ack d7 output based on the value set in acke in advance 6789 23 d6 d5 1 sda0 (sda1) 362 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (3) register setting the i 2 c mode setting is performed by serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specification register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim0 to 00h. r/w csim01 csim00 serial interface channel 0 clock selection 0 input clock from off-chip to scl pin 1 0 8-bit timer register 2 (tm2) output note 2 1 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operation start si0/sb0/sda0/ so0/sb1/sda1/ sck0/scl/p27 04 03 02 mode bit p25 pin function p26 pin function pin function 0 3-wire serial i/o mode (see 17.4.2 operation in 3-wire serial i/o mode ) 11 0 0 0 0 1 2-wire msb p25 sb1/sda1 sck0/scl note 3 note 3 serial i/o or (cmos i/o) n-ch open- n-ch open- i 2 c bus mode drain i/o drain i/o 11 1 0 0 0 1 2-wire msb sb0/sda0 p26 sck0/scl note 3 note 3 serial i/o or n-ch open- (cmos i/o) n-ch open- i 2 c bus mode drain i/o drain i/o r/w wup wake-up function control note 4 0 interrupt request signal generation with each serial transfer in any mode 1 in i 2 c bus mode, interrupt request signal is generated when the address data received after start condition detection (when cmdd = 1) matches data in slave address register (sva). r coi slave address comparison result flag note 5 0 slave address register (sva) not equal to data in serial i/o shift register 0 (sio0) 1 slave address register (sva) equal to data in serial i/o shift register 0 (sio0) r/w csie0 serial interface channel 0 operation control 0 operation stopped. 1 operation enabled. notes 1. bit 6 (coi) is a read-only bit. 2. in the i 2 c bus mode, the clock frequency is 1/16 of the clock frequency output by to2. 3. can be used freely as a port. 4. to use the wakeup function (wup = 1), set bit 5 (sic) of the interrupt timing specification register (sint) to 1. do not execute an instruction that writes serial i/o shift register 0 (sio0) while wup = 1. 5. when csie0 = 0, coi is 0. remark : don t care pm : port mode register p : port output latch <6><5>43210 <7> symbol csim0 ff60h 00h r/w note 1 address after reset r/w csie0 coi wup csim04 csim03 csim02 csim01 csim00 363 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sbic to 00h. r/w relt use for stop condition output. when relt = 1, the so0 latch is set to 1. after the so0 latch is set, relt is automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w cmdt use for start condition output. when cmdt = 1, the so0 latch is cleared to 0. after the so0 latch is cleared, cmdt is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r reld stop condition detection 0 clear conditions when transfer start instruction is executed if sio0 and sva values do not match in address reception when csie0 = 0 when reset input is applied 1 setting condition when stop condition is detected r cmdd start condition detection 0 clear conditions when transfer start instruction is executed when stop condition is detected when csie0 = 0 when reset input is applied 1 setting condition when start condition is detected r/w ackt sda0 (sda1) is set to low after the set instruction execution (ackt = 1) before the next scl falling edge. used for generating an ack signal by software if the 8-clock wait mode is selected. cleared to 0 if csie0 = 0 when a transfer by the serial interface is started. r/w acke acknowledge signal automatic output control note 2 0 disabled (with ackt enabled). used when receiving data in the 8-clock wait mode or when transmitting data. note 3 1 enabled. after completion of transfer, the acknowledge signal is output in acke is synchronization with the 9th falling edge of the scl clock (automatically output when acke = 1). however, acke is not automatically cleared to 0 after acknowledge signal is output. it is used for reception when the 9-clock wait mode is selected. r ackd acknowledge detection 0 clear conditions when transfer start instruction is executed when csie0 = 0 when reset input is applied 1 set conditions when the acknowledge signal is detected at the rising edge of scl clock after completion of transfer r/w control of n-ch open-drain output for transmission in i 2 c bus mode note 5 bsye 0 output enabled (transmission) 1 output disabled (reception) notes 1. bits 2, 3, and 6 (reld, cmdd, ackd) are read-only bits. 2. this setting must be performed prior to transfer start. 3. in the 8-clock wait mode, use ackt for output of the acknowledge signal after normal data reception. 4. the busy mode can be released by the start of a serial interface transfer or reception of an address signal. however, the bsye flag is not cleared. 5. when using the wakeup function, be sure to set bsye to 1. remark csie0: bit 7 of serial operating mode register 0 (csim0) note 4 <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ff61h 00h r/w note 1 address after reset r/w ackt cmdd reld cmdt relt 364 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (c) interrupt timing specification register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sint to 00h. r/w wat1 wat0 interrupt control by wait note 2 0 0 interrupt service request is generated on rise of 8th sck0 clock cycle (clock output is high impedance). 0 1 setting prohibited 1 0 used in i 2 c bus mode (8-clock wait) generates an interrupt service request on rise of 8th scl clock cycle. (in case of master device, scl pin is driven low after output of 8 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 8 clock cycles, to require the wait state.) 1 1 used in i 2 c bus mode (9-clock wait) generates an interrupt service request on rise of 9th scl clock cycle. (in case of master device, scl pin is driven low after output of 9 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 9 clock cycles, to require the wait state.) r/w wrel wait release control 0 indicates that the wait state has been released. 1 releases the wait state. automatically cleared to 0 after releasing the wait state. this bit is used to release the wait state set by means of wat0 and wat1. r/w clc clock level control 0 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is driven low. 1 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is set to high impedance. (clock line is held high.) used by master device to generate the start condition and stop condition signals. r/w svam sva bits used as slave address 0 bits 0 to 7 1 bits 1 to 7 r/w sic intcsi0 interrupt source selection note 3 0 csiif0 is set to 1 after end of serial interface channel 0 transfer. 1 csiif0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected. r cld scl pin level note 4 0 low level 1 high level notes 1. bit 6 (cld) is read-only. 2. when the i 2 c bus mode is used, be sure to set wat0 and wat1 to 1 and 0, or 1 and 1, respectively. 3. when using the wakeup function in i 2 c mode, be sure to set sic to 1. 4. when csie0 = 0, cld is 0. remark sva: slave address register csiif0: interrupt request flag corresponding to intcsi0 csie0: bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic ff63h 00h r/w note 1 address after reset r/w svam clc wrel wat1 wat0 365 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (4) various signals a list of signals in the i 2 c bus mode is given in table 17-4. table 17-4. signals in i 2 c bus mode signal name description start condition definition: sda0 (sda1) falling edge when scl is high note 1 function: indicates that serial communication starts and subsequent data is address data. signaled by: master signaled when: cmdt is set. affected flag(s): cmdd (is set.) stop condition definition: sda0 (sda1) rising edge when scl is high note 1 function: indicates end of serial transmission. signaled by: master signaled when: relt is set. affected flag(s): reld (is set) and cmdd (is cleared) acknowledge signal (ack) definition: low level of sda0 (sda1) pin during one scl clock cycle after serial reception function: indicates completion of reception of 1 byte. signaled by: master or slave signaled when: ackt is set with acke = 1. affected flag(s): ackd (is set.) wait (wait) definition: low-level signal output to scl function: indicates state in which serial reception is not possible. signaled by: slave signaled when: wat1, wat0 = 1x. affected flag(s): none serial clock (scl) definition: synchronization clock for output of various signals function: serial communication synchronization signal. signaled by: master signaled when: see note 2 below. affected flag(s): csiif0. also see note 3 below. address (a6 to a0) definition: 7-bit data synchronized with scl immediately after start condition signal function: indicates address value for specification of slave on serial bus. signaled by: master signaled when: see note 2 below. affected flag(s): csiif0. also see note 3 below. transfer direction (r/w) definition: 1-bit data output in synchronization with scl after address output function: indicates whether data transmission or reception is to be performed. signaled by: master signaled when: see note 2 below. affected flag(s): csiif0. also see note 3 below. data (d7 to d0) definition: 8-bit data synchronized with scl, not immediately after start condition function: contains data to be actually sent. signaled by: master or slave signaled when: see note 2 below. affected flag(s): csiif0. also see note 3 below. notes 1. the level of the serial clock can be controlled with bit 3 (clc) of interrupt timing specify register (sint). 2. execution of instruction to write data to sio0 when csie0 = 1 (serial transfer start directive). in the wait state, the serial transfer operation will be started after the wait state is released. 3. if the 8-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 8th clock cycle of scl. if the 9-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 9th clock cycle of scl. csiif0 is set if an address is received and that address matches the value of the slave address register (sva) when wup = 1, or if the stop condition is detected. 366 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (5) pin configurations the configurations of the serial clock pin scl and the serial data bus pins sda0 (sda1) are shown below. (a) scl pin for serial clock input/output alternate-function pin. <1> master ..... n-ch open-drain output <2> slave ....... schmitt input (b) sda0 (sda1) serial data i/o alternate-function pin. uses n-ch open-drain output and schmitt-input buffers for both master and slave devices. note that pull-up resistors are required to be connected to both the serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. figure 17-21. pin configuration caution to receive data, the n-ch open-drain output must made to go into a high-impedance state. therefore, set bit 7 (bsye) of the serial bus interface control register (sbic) to 1 in advance, and write ffh to serial i/o shift register 0 (sio0). when the wakeup function is used (by setting bit 5 (wup) of serial operating mode register 0 (csim0)), however, do not write ffh to sio0 before reception. even if ffh is not written to sio0, the n-ch open-drain output always goes into a high-impedance state. (6) address match detection method in the i 2 c mode, the master can select a specific slave device by sending slave address data. a match of the addresses can be automatically detected by hardware. csiif0 is set if the slave address transmitted by the master matches the value set to the slave address register (sva) when a slave device address has a slave register (sva), and the wakeup function specification bit (wup) = 1 (csiif0 is also set when the stop condition is detected). when using the wakeup function, set sic to 1. caution slave selection/non-selection is detected by matching of the data (address) received after the start condition. for this match detection, the match interrupt request (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. v dd0 v dd0 scl sda0 (sda1) master device clock output (clock input) data output data input slave devices (clock output) clock input data output data input scl sda0 (sda1) v ss0 v ss0 v ss0 v ss0 367 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (7) error detection in the i 2 c bus mode, transmission error detection can be performed by the following methods because the serial bus sda0 (sda1) status during transmission is also taken into the serial i/o shift register 0 (sio0) register of the transmitting device. (a) comparison of sio0 data before and after transmission in this case, a transmission error is judged to have occurred if the two data values are different. (b) using the slave address register (sva) transmit data is set in sio0 and sva before transmission is performed. after transmission, the coi bit (match signal from the address comparator) of serial operating mode register 0 (csim0) is tested: 1 indicates normal transmission, and 0 indicates a transmission error. (8) communication operation in the i 2 c bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. after the slave address data, the master sends the r/w bit which indicates the data transfer direction, and starts serial communication with the selected slave device. data communication timing charts are shown in figures 17-22 and 17-23 . in the transmitting device, serial i/o shift register 0 (sio0) shifts transmission data to the so latch in synchronization with the falling edge of the serial clock (scl), the so0 latch outputs the data on an msb- first basis from the sda0 or sda1 pin to the receiving device. in the receiving device, the data input from the sda0 or sda1 pin is taken into the sio0 in synchronization with the rising edge of scl. 368 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-22. data transmission from master to slave (both master and slave selected 9-clock wait) (1/3) (a) start condition to address l l l 1 a5 a4 a3 a2 a1 a0 w ack a6 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l sio0 address master device operation transfer line slave device operation sio0 data h l l l l l l l h h h h sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 369 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-22. data transmission from master to slave (both master and slave selected 9-clock wait) (2/3) (b) data l l l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l l l sio0 address master device operation transfer line sio0 data h l l l l l l l h h h h sio0 ffh sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 slave device operation 370 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-22. data transmission from master to slave (both master and slave selected 9-clock wait) (3/3) (c) stop condition l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 a6 a5 a4 a3 1234 9 l l l l sio0 data master device operation transfer line sio0 address h l l l l h h h sio0 ffh write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 slave device operation sio0 ffh 371 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-23. data transmission from slave to master (both master and slave selected 9-clock wait) (1/3) (a) start condition to address l l l 1 a0 a1 a2 a3 a4 a5 a6 r ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 address master device operation transfer line sio0 ffh h l l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 slave device operation sio0 data 372 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-23. data transmission from slave to master (both master and slave selected 9-clock wait) (2/3) (b) data l l l l h h l 1 d1 d0 d2 d3 d4 d5 d6 d7 ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 ffh master device operation transfer line sio0 ffh h l l l l l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 slave device operation sio0 data sio0 data 373 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-23. data transmission from slave to master (both master and slave selected 9-clock wait) (3/3) (c) stop condition l l 1 d1 d0 d2 d3 d4 d5 d6 d7 nak 2345678 a6 a5 a4 a3 1234 9 l l sio0 ffh master device operation transfer line sio0 address h l l l l l l h h write sio0 coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 slave device operation sio0 data 374 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (9) transfer start a serial transfer is started by setting transfer data in serial i/o shift register 0 (sio0) if the following two conditions have been satisfied. the serial interface channel 0 operation control bit (csie0) = 1. after an 8-bit serial transfer, the internal serial clock is stopped or scl is low. cautions 1. be sure to set csie0 to 1 before writing data in sio0. setting csie0 to 1 after writing data in sio0 does not initiate transfer operation. 2. because the n-ch open-drain output must made to go into a high-impedance state during data reception, set bit 7 (bsye) of the serial bus interface control register (sbic) to 1 before writing ffh to sio0. do not write ffh to sio0 before reception when the wakeup function is used (by setting bit 5 (wup) of serial operating mode register 0 (csim0)). even if ffh is not written to sio0, the n-ch open-drain output always goes into a high-impedance state. 3. if data is written to sio0 while the slave is in the wait state, that data is held. the transfer is started when scl is output after the wait state is cleared. when an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (csiif0) is set. 17.4.5 cautions on use of i 2 c bus mode (1) start condition output (master) the scl pin normally outputs a low-level signal when no serial clock is output. it is necessary to change the scl pin to high in order to output a start condition signal. set clc to 1 in the interrupt timing specification register (sint) to drive the scl pin high. after setting clc, clear clc to 0 and return the scl pin to low. if clc remains 1, no serial clock is output. if it is the master device which outputs the start condition and stop condition signals, confirm that cld is set to 1 after setting clc to 1; a slave device may have set scl to low (wait state). figure 17-24. start condition output scl clc cmdt cld sda0 (sda1) 375 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (2) slave wait release (slave transmission) slave wait status is released by wrel flag (bit 2 of interrupt timing specification register (sint)) setting or execution of a serial i/o shift register 0 (sio0) write instruction. if the slave sends data, the wait is immediately released by execution of an sio0 write instruction and the clock rises without the start transmission bit being output in the data line. therefore, as shown in figure 17-25, data should be transmitted by manipulating the p27 output latch through the program. at this time, control the low-level width ( a in figure 17-25 ) of the first serial clock at the timing used for setting the p27 output latch to 1 after execution of an sio0 write instruction. in addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the wrel flag of sint and release the wait. for this timing, see figure 17-23 . figure 17-25. slave wait release (transmission) writing ffh to sio0 setting csiif0 setting ackd serial reception 9 a 23 a0 r ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial transmission write data to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0 (sda1) 376 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (3) slave wait release (slave reception) the slave is released from the wait status when the wrel flag (bit 2 of the interrupt timing specification register (sint)) is set or when an instruction that writes data to serial i/o shift register 0 (sio0) is executed. when the slave receives data, the first bit of the data sent from the master may not be received if the scl line immediately goes into a high-impedance state after an instruction that writes data to sio has been executed. this is because sio0 does not start operating if the scl line is in the high-impedance state while the instruction that writes data to sio0 is being executed (until the next instruction is executed). therefore, receive the data by manipulating the output latch of p27 by program, as shown in figure 17-26. for this timing, see figure 17-22 . figure 17-26. slave wait release (reception) writing data to sio0 setting csiif0 setting ackd serial transmission 923 a0 ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial reception write ffh to sio0 p27 output latch 0 wait release software operation hardware operation scl sda0 (sda1) software operation hardware operation 1 w master device operation transfer line slave device operation 377 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud (4) reception completion of slave in the reception completion processing of the slave, check bit 3 (cmdd) of the serial bus interface control register (sbic) and bit 6 (coi) of serial operation mode register 0 (csim0) (when cmdd = 1). this is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore the wakeup condition cannot be used when the slave receives an undefined number of data from the master. 17.4.6 restrictions in i 2 c bus mode 1 the following restrictions are applied to the pd780058y subseries. restrictions when used as slave device in i 2 c bus mode target device: pd780053y, 780054y, 780055y, 780056y, 780058by, 78f0058y, ie-780308-r-em, ie-780308-ns-em1 description: if the wakeup function is executed (by setting bit 5 of serial operating mode register 0 (csim0) to 1) in the serial transfer status note , the pd780058y subseries checks the address of the data between the other slaves and the master. if that data happens to match the slave address of the pd780058y subseries, the pd780058y subseries takes part in communication, destroying the communication data. note the serial transfer status is the status from when data is written to serial i/o shift register 0 (sio0) until the interrupt request flag (csiif0) is set to 1 by completion of the serial transfer. preventive measure: the above phenomenon can be avoided by modifying the program. before executing the wakeup function, execute the following program that clears the serial transfer status. when executing the wakeup function, do not execute an instruction that writes data to sio0. even if such an instruction is not executed, data can be received when the wakeup function is executed. this program releases the serial transfer status. to release the serial transfer status, serial interface channel 0 must be disabled once (by clearing the csie0 flag (bit 7 of the serial operating mode register (csim0) to 0). if serial interface channel 0 is disabled in the i 2 c bus mode, however, the scl pin outputs a high level, and the sda0 (sda1) pin outputs a low level, affecting communication of the i 2 c bus. therefore, this program makes the scl and sda0 (sda1) pins go into a high-impedance state to prevent the i 2 c bus from being affected. in this example, the sda0 (/p25) pin is used as a serial data input/output pin. when sda1 (/p26) is used, take p2.5 and pm2.5 in the program example below as p2.6 and pm2.6. for the timing of each signal when this program is executed, see figure 17-22 . 378 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud example of program releasing serial transfer status set1 p2.5; <1> set1 pm2.5; <2> set1 pm2.7; <3> clr1 csie0; <4> set1 csie0; <5> set1 relt; <6> clr1 pm2.7; <7> clr1 p2.5; <8> clr1 pm2.5; <9> <1> this instruction prevents the sda0 pin from outputting a low level when the i 2 c bus mode is restored by instruction <5> . the output of the sda0 pin goes into a high-impedance state. <2> this instruction sets the p25 (/sda0) pin in the input mode to protect the sda0 line from adverse influence when the port mode is set by instruction <4> . the p25 pin is set in the input mode when instruction <2> is executed. <3> this instruction sets the p27 (/scl) pin in the input mode to protect the scl line from adverse influence when the port mode is set by instruction <4> . the p27 pin is set in the input mode when instruction <3> is executed. <4> this instruction changes the mode from i 2 c bus mode to port mode. <5> this instruction restores the i 2 c bus mode from the port mode. <6> this instruction prevents the sda0 pin from outputting a low level when instruction <8> is executed. <7> this instruction sets the p27 pin in the output mode because the p27 pin must be in the output mode in the i 2 c bus mode. <8> this instruction clears the output latch of the p25 pin to 0 because the output latch of the p25 pin must be cleared to 0 in the i 2 c bus mode. <9> this instruction sets the p25 pin in the output mode because the p25 pin must be in the output mode in the i 2 c bus mode. remark relt: bit 0 of serial bus interface control register (sbic) 379 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4.7 restrictions in i 2 c bus mode 2 when using the i 2 c bus mode under the following conditions, the stop condition is detected and an interrupt occurs when csie0 is set to 1. to enable the operation (by setting csie0 to 1), therefore, perform the following processing. condition: if a low level is used when csie0 is set to 1 when using the p26/sda as the sda line and p25/sda0 as an input port (1) when operation is enabled set1 csimk0 ; disables intcsi0 interrupt. set1 csie0 ; enables iic operation. clr1 csiif0 ; clears intcsi0 interrupt request flag. clr1 csimk0 ; enables intcsi0 interrupt. cautions 1. after that, reld = 1 (stop condition is detected) until data that does not match the source station slave address (sva) is received. 2. even if a start condition is satisfied while reld = 1 (stop condition is detected), the interrupt occurs if it is enabled and cmdd = 1 (start condition is detected). (2) when using as slave device in i 2 c bus mode (if restrictions in 17.4.6 apply) example of program releasing serial transfer status set1 csimk0 ; disables intcsi0 interrupt. set1 p2.6 set1 pm2.6 set1 pm2.7 clr1 csie0 ; stops iic operation. set1 csie0 ; enables iic operation. clr1 csiif0 ; clears intcsi0 interrupt request flag. clr1 csimk0 ; enables intcsi0 interrupt. set1 relt clr1 pm2.7 clr1 p2.6 clr1 pm2.6 cautions 1. after that, reld = 1 (stop condition is detected) until data that does not match the source station slave address (sva) is received. 2. even if a start condition is satisfied while reld = 1 (stop condition is detected), the interrupt occurs if it is enabled and cmdd = 1 (start condition is detected). 380 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud 17.4.8 sck0/scl/p27 pin output manipulation the sck0/scl/p27 pin can execute static output via software, in addition to outputting the normal serial clock. the value of the serial clock can also be arbitrarily set by software (the si0/sb0/sda0 and so0/sb1/sda1 pins are controlled by bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic)). the sck0/scl/p27 pin output should be manipulated as described below. (1) in 3-wire serial i/o mode and 2-wire serial i/o mode the output level of the sck0/scl/p27 pin is manipulated by the p27 output latch. <1> set serial operating mode register 0 (csim0) (sck0 pin: output mode, serial operation: enabled). sck0 = 1 while serial transfer is stopped. <2> manipulate the contents of the p27 output latch by executing a bit manipulation instruction. figure 17-27. sck0/scl/p27 pin configuration (2) in i 2 c bus mode the output level of the sck0/scl/p27 pin is manipulated by the clc bit of the interrupt timing specification register (sint). <1> set serial operating mode register 0 (csim0) (scl pin: output mode, serial operation: enabled). set the p27 output latch to 1. scl = 0 while serial transfer is stopped. <2> manipulate the clc bit of sint by executing a bit manipulation instruction. figure 17-28. sck0/scl/p27 pin configuration note the level of the scl signal is in accordance with the contents of the logic circuits shown in figure 17-29 . sck0/scl/p27 to internal logic p27 output latch csie0 = 1 and csim01, csim00 are 1, 0 or 1, 1, respectively sck0 (1 while transfer is stopped) from serial clock controller manipulated by bit manipulation instruction sck0/scl/p27 to internal logic p27 output latch csie0 = 1 and csim01 and csim00 are 1, 0 or 1, 1, respectively scl note set 1 from serial clock controller 381 chapter 17 serial interface channel 0 ( pd780058y subseries) user's manual u12013ej3v2ud figure 17-29. logic circuit of scl signal remarks 1. this figure indicates the relationship of the signals and does not indicate the internal circuit. 2. clc: bit 3 of interrupt timing specification register (sint) clc (manipulated by bit manipulation instruction) wait request signal serial clock (low while transfer is stopped) scl 382 user's manual u12013ej3v2ud chapter 18 serial interface channel 1 18.1 functions of serial interface channel 1 serial interface channel 1 employs the following three modes. operation stop mode 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) 3-wire serial i/o mode (msb-/lsb-first switchable) this mode is used for 8-bit data transfer using three lines: a serial clock (sck1), serial output (so1), and serial input (si1). the 3-wire serial i/o mode enables simultaneous transmission/reception and so decreases the data transfer processing time. since the start bit of 8-bit data to undergo serial transfer is switchable between the msb and lsb, connection is enabled with either start bit device. the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous serial interface such as the 75x/xl, 78k, and 17k series. (3) 3-wire serial i/o mode with automatic transmit/receive function (msb-/lsb-first switchable) this mode is equivalent to the 3-wire serial i/o mode with the addition of an automatic transmit/receive function. the automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. this function enables the hardware to transmit/receive data to/from the osd (on screen display) device and a device with built-in display controller/driver independently of the cpu, thus alleviating the software load. caution when using the p23/stb/txd1 and p24/busy/rxd1 pins in the asynchronous serial interface (uart) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid. 383 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud 18.2 configuration of serial interface channel 1 serial interface channel 1 consists of the following hardware. table 18-1. configuration of serial interface channel 1 item configuration registers serial i/o shift register 1 (sio1) automatic data transmit/receive address pointer (adtp) control registers timer clock select register 3 (tcl3) serial operating mode register 1 (csim1) automatic data transmit/receive control register (adtc) automatic data transmit/receive interval specification register (adti) port mode register 2 (pm2) note note see figures 6-5 and 6-7 block diagram of p20, p21, and p23 to p26 and figures 6-6 and 6-8 block diagram of p22 and p27 . 384 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-1. block diagram of serial interface channel 1 re arld erce err trf strb busy 1 busy 0 internal bus automatic data transmit/receive control register serial operating mode register 1 adti 7 adti 4 adti 3 adti 2 adti 1 adti 0 5-bit counter serial i/o shift register 1 (sio1) hand- shake serial clock counter selector selector so1/ p21 pm21 p21 output latch dir dir buffer ram automatic data transmit/receive address pointer (adtp) sck1/ p22 pm22 internal bus trf p22 output latch match adti0 to adti4 selector to2 intcsi1 clear sioi write q r s selector tcl 37 tcl 36 tcl 35 tcl 34 4 timer clock select register 3 f xx /2 to f xx /2 8 internal bus arld csie1 dir ate csim 11 csim 10 ate si1/ p20 stb/ txd1/p23 pm23 busy/ rxd1/p24 automatic data transmit/receive interval specify register 385 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (1) serial i/o shift register 1 (sio1) this is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/ reception (shift operations) in synchronization with the serial clock. sio1 is set with an 8-bit memory manipulation instruction. when the value in bit 7 (csie1) of serial operating mode register 1 (csim1) is 1, writing data to sio1 starts serial operation. in transmission, data written to sio1 is output to the serial output (so1). in reception, data is read from the serial input (si1) to sio1. reset input makes sio1 undefined. caution do not write data to sio1 while the automatic transmit/receive function is activated. (2) automatic data transmit/receive address pointer (adtp) this register stores the value of (the number of transmit data bytes 1) while the automatic transmit/receive function is activated. as data is transferred/received, the pointer is automatically decremented. adtp is set with an 8-bit memory manipulation instruction. the higher 3 bits must be cleared to 0. reset input clears adtp to 00h. caution do not write data to adtp while the automatic transmit/receive function is activated. (3) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. 386 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud 18.3 control registers of serial interface channel 1 the following four registers are used to control serial interface channel 1. timer clock select register 3 (tcl3) serial operating mode register 1 (csim1) automatic data transmit/receive control register (adtc) automatic data transmit/receive interval specification register (adti) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 1. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. remark besides setting the serial clock of serial interface channel 1, tcl3 sets the serial clock of serial interface channel 0. 387 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-2. format of timer clock select register 3 caution when rewriting other data to tcl3 , stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w 388 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (2) serial operating mode register 1 (csim1) this register sets the serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. figure 18-3. format of serial operation mode register 1 notes 1. if the external clock input has been selected with csim11 cleared to 0, clear bit 1 (busy1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. 2. can be used freely as a port function. 3. can be used as p20 (cmos i/o) when only transmission is performed (clear bit 7 (re) of adtc to 0). remark : don t care pm : port mode register p : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection external clock input to sck1 pin note 1 8-bit timer register 2 (tm2) output sck1 (input) 1 clock specified by bits 4 to 7 of timer clock select register 3 (tcl3) csie1 0 csim10 0 1 ff68h 00h r/w address after reset r/w csim11 p20 pm21 p21 pm22 note 3 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function 1 0 1 0 001 1 note 2 note 2 note 2 note 2 count operation si1 (input) operation stop clear p20 (cmos i/o) p22 (cmos i/o) ate 0 1 serial interface channel 1 operating mode selection 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function dir 0 1 start bit msb lsb si1 pin function si1/p20 (input) so1 pin function so1 (cmos output) pm20 so1/p21 pin function so1 (cmos output) p21 (cmos i/o) sck1 (cmos output) 1 note 2 note 2 note 3 note 3 p22 389 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (3) automatic data transmit/receive control register (adtc) this register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. adtc is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adtc to 00h. figure 18-4. format of automatic data transmit/receive control register notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. the termination of automatic transmission/reception should be judged by using trf, not csiif1 (interrupt request flag). cautions 1. when an external clock input is selected by clearing bit 1 (csim11) of serial operating mode register 1 (csim1) to 0, clear strb and busy1 of adtc to 0, 0. 2. when using the p23/stb/txd1 and p24/busy/rxd1 pins in the asynchronous serial interface (uart) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid. remark : don t care <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff69h 00h r/w note 1 address after reset r/w busy1 0 1 1 busy input control not using busy input busy input enabled (active high) busy input enabled (active low) busy0 0 1 strb 0 1 strobe output control strobe output disabled strobe output enabled trf 1 status of automatic transmit/receive function note 2 detection of termination of automatic transmission/ reception. (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) during automatic transmission/reception (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection of automatic transmit/receive function no error (this bit is set to 0 when data is written to sio1.) error occurred r/w arld 0 1 operating mode selection of automatic transmit/receive function one-shot mode repetitive one-shot mode r/w re 0 1 receive control of automatic transmit/receive function receive disabled receive enabled r/w erce 0 error check control of automatic transmit/receive function error check disabled error check enabled (only when busy1 = 1) 0 1 390 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (4) automatic data transmit/receive interval specification register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adti to 00h. figure 18-5. format of automatic data transmit/receive interval specification register (1/4) notes 1. the interval is dependent only on the cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + , maximum = (n + 1) + + cautions 1. do not write anything to adti while automatic transmission/reception is in progress (bit 3 (trf) of the adtc register = 1). 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 28 0.5 f xx f xx f sck 2 6 f xx 36 f xx 1.5 f sck data transfer interval specification (f xx = 5.0 mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 18.4 s + 0.5/f sck 31.2 s + 0.5/f sck 44.0 s + 0.5/f sck 56.8 s + 0.5/f sck 69.6 s + 0.5/f sck 82.4 s + 0.5/f sck 95.2 s + 0.5/f sck 108.0 s + 0.5/f sck 120.8 s + 0.5/f sck 133.6 s + 0.5/f sck 146.4 s + 0.5/f sck 159.2 s + 0.5/f sck 172.0 s + 0.5/f sck 184.8 s + 0.5/f sck 197.6 s + 0.5/f sck 210.4 s + 0.5/f sck maximum note 2 20.0 s + 1.5/f sck 32.8 s + 1.5/f sck 45.6 s + 1.5/f sck 58.4 s + 1.5/f sck 71.2 s + 1.5/f sck 84.0 s + 1.5/f sck 96.8 s + 1.5/f sck 109.6 s + 1.5/f sck 122.4 s + 1.5/f sck 135.2 s + 1.5/f sck 148.0 s + 1.5/f sck 160.8 s + 1.5/f sck 173.6 s + 1.5/f sck 186.4 s + 1.5/f sck 199.2 s + 1.5/f sck 212.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 391 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-5. format of automatic data transmit/receive interval specification register (2/4) note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 28 0.5 f xx f xx f sck 2 6 36 1.5 f xx f xx f sck data transfer interval specification (f xx = 5.0 mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 223.2 s + 0.5/f sck 236.0 s + 0.5/f sck 248.8 s + 0.5/f sck 261.6 s + 0.5/f sck 274.4 s + 0.5/f sck 287.2 s + 0.5/f sck 300.0 s + 0.5/f sck 312.8 s + 0.5/f sck 325.6 s + 0.5/f sck 338.4 s + 0.5/f sck 351.2 s + 0.5/f sck 364.0 s + 0.5/f sck 376.8 s + 0.5/f sck 389.6 s + 0.5/f sck 402.4 s + 0.5/f sck 415.2 s + 0.5/f sck maximum note 224.8 s + 1.5/f sck 237.6 s + 1.5/f sck 250.4 s + 1.5/f sck 263.2 s + 1.5/f sck 276.0 s + 1.5/f sck 288.8 s + 1.5/f sck 301.6 s + 1.5/f sck 314.4 s + 1.5/f sck 327.2 s + 1.5/f sck 340.0 s + 1.5/f sck 352.8 s + 1.5/f sck 365.6 s + 1.5/f sck 378.4 s + 1.5/f sck 391.2 s + 1.5/f sck 404.0 s + 1.5/f sck 416.8 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 392 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-5. format of automatic data transmit/receive interval specification register (3/4) notes 1. the interval is dependent only on the cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 28 f xx f xx 2 6 36 f xx f xx 0.5 f sck 1.5 f sck data transfer interval specification (f xx = 2.5 mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 36.8 s + 0.5/f sck 62.4 s + 0.5/f sck 88.0 s + 0.5/f sck 113.6 s + 0.5/f sck 139.2 s + 0.5/f sck 164.8 s + 0.5/f sck 190.4 s + 0.5/f sck 216.0 s + 0.5/f sck 241.6 s + 0.5/f sck 267.2 s + 0.5/f sck 292.8 s + 0.5/f sck 318.4 s + 0.5/f sck 344.0 s + 0.5/f sck 369.6 s + 0.5/f sck 395.2 s + 0.5/f sck 420.8 s + 0.5/f sck maximum note 2 40.0 s + 1.5/f sck 65.6 s + 1.5/f sck 91.2 s + 1.5/f sck 116.8 s + 1.5/f sck 142.4 s + 1.5/f sck 168.0 s + 1.5/f sck 193.6 s + 1.5/f sck 219.2 s + 1.5/f sck 244.8 s + 1.5/f sck 270.4 s + 1.5/f sck 296.0 s + 1.5/f sck 321.6 s + 1.5/f sck 347.2 s + 1.5/f sck 372.8 s + 1.5/f sck 398.4 s + 1.5/f sck 424.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 393 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-5. format of automatic data transmit/receive interval specification register (4/4) note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 28 0.5 f xx f xx f sck 2 6 36 1.5 f xx f xx f sck data transfer interval specification (f xx = 2.5 mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 446.4 s + 0.5/f sck 472.0 s + 0.5/f sck 497.6 s + 0.5/f sck 523.2 s + 0.5/f sck 548.8 s + 0.5/f sck 574.4 s + 0.5/f sck 600.0 s + 0.5/f sck 625.6 s + 0.5/f sck 651.2 s + 0.5/f sck 676.8 s + 0.5/f sck 702.4 s + 0.5/f sck 728.0 s + 0.5/f sck 753.6 s + 0.5/f sck 779.2 s + 0.5/f sck 804.8 s + 0.5/f sck 830.4 s + 0.5/f sck maximum note 449.6 s + 1.5/f sck 475.2 s + 1.5/f sck 500.8 s + 1.5/f sck 526.4 s + 1.5/f sck 552.0 s + 1.5/f sck 577.6 s + 1.5/f sck 603.2 s + 1.5/f sck 628.8 s + 1.5/f sck 654.4 s + 1.5/f sck 680.0 s + 1.5/f sck 705.6 s + 1.5/f sck 731.2 s + 1.5/f sck 756.8 s + 1.5/f sck 782.4 s + 1.5/f sck 808.0 s + 1.5/f sck 833.6 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 394 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud 18.4 operations of serial interface channel 1 the following three operating modes are available for serial interface channel 1. operation stop mode 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function 18.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. serial i/o shift register 1 (sio1) does not carry out shift operations either, and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p20/si1, p21/so1, p22/sck1, p23/stb/txd1, and p24/busy/rxd1 pins can be used as ordinary i/o ports. (1) register setting the operation stop mode is set by serial operating mode register 1 (csim1). csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. notes 1. can be used freely as a port function. 2. can be used as p20 (cmos i/o) when only transmission is performed (clear bit 7 (re) of the automatic data transmit/receive control register (adtc) to 0). remark : don t care pm : port mode register p : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 sck1 (input) csie1 0 ff68h 00h r/w address after reset r/w csim11 p20 pm21 p21 pm22 note 2 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function 1 0 1 0 001 1 note 1 note 1 note 1 note 1 count operation si1 (input) operation stop clear p20 (cmos i/o) p22 (cmos i/o) pm20 so1/p21 pin function so1 (cmos output) p21 (cmos i/o) sck1 (cmos output) 1 note 1 note 1 note 2 note 2 p22 395 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud 18.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is useful for connection of peripheral i/o units and display controllers which incorporate a conventional clocked serial interface such as the 75x/xl, 78k and 17k series. communication is carried out using the three lines of the serial clock (sck1), serial output (so1) and serial input (si1). (1) register setting the 3-wire serial i/o mode is set by serial operating mode register 1 (csim1). csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. note if the external clock input has been selected by setting csim11 to 0, set bit 1 (busy1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. remark : don t care 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection external clock input to sck1 pin note 8-bit timer register 2 (tm2) output 1 clock specified by bits 4 to 7 of timer clock select register 3 (tcl3) csim10 0 1 ff68h 00h r/w address after reset r/w ate 0 1 serial interface channel 1 operating mode selection 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function dir 0 1 start bit msb lsb so1 pin function si1/p20 (input) so1 pin function so1 (cmos output) 396 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operations of serial i/o shift register 1 (sio1) are carried out at the falling edge of the serial clock sck1. the transmit data is held in the so1 latch and is output from the so1 pin. the receive data input to the si1 pin is latched into sio1 at the rising edge of sck1. upon termination of 8-bit transfer, the sio1 operation stops automatically and the interrupt request flag (csiif1) is set. figure 18-6. 3-wire serial i/o mode timing caution the so1 pin becomes low level by writing sio1. si1 sck1 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so1 do7 do6 do5 do4 do3 do2 do1 do0 csiif1 transfer start at the falling edge of sck1 end of transfer sio1 write notes 1. can be used freely as a port function. 2. can be used as p20 (cmos input/output) when only transmission is performed (clear bit 7 (re) of adtc to 0). remark : don t care pm : port mode register p : port output latch operation enable sck1 (input) csie1 0 csim11 p20 pm21 p21 pm22 note 2 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function 1 0 1 0 001 1 note 1 note 1 note 1 note 1 count operation si1 (input) operation stop clear p20 (cmos i/o) p22 (cmos i/o) pm20 so1/p21 pin function so1 (cmos output) p21 (cmos i/o) sck1 (cmos output) 1 note 1 note 1 note 2 note 2 p22 397 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (3) msb/lsb switching as the start bit in 3-wire serial i/o mode, it is possible to select transfer to start from the msb or lsb. figure 18-7 shows the configuration of serial i/o shift register 1 (sio1) and the internal bus. as shown in the figure, the msb/lsb can be read or written in reverse form. msb/lsb switching as the start bit can be specified by bit 6 (dir) of serial operating mode register 1 (csim1). figure 18-7. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data write to sio1. the sio1 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to serial i/o shift register 1 (sio1) when the following two conditions are satisfied. serial interface channel 1 operation control bit (csie1) = 1 internal serial clock is stopped or sck1 is a high level after 8-bit serial transfer. caution if csie1 is set to 1 after data write to sio1, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif1) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si1 shift register 1 (sio1) read/write gate so1 sck1 dq so1 latch 398 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud 18.4.3 3-wire serial i/o mode operation with automatic transmit/receive function this 3-wire serial i/o mode is used for transmission/reception of a maximum of 32 bytes of data without the use of software. once transfer is started, the set number of bytes of the data prestored in the ram can be transmitted, and the set number of bytes of data can be received and stored in the ram. handshake signals (stb and busy) are supported by hardware to transmit/receive data continuously. an osd (on screen display) lsi and peripheral lsi including an lcd controller/driver can thus be connected without difficulty. (1) register setting the 3-wire serial i/o mode with automatic transmit/receive function is set by serial operating mode register 1 (csim1), the automatic data transmit/receive control register (adtc) and the automatic data transmit/ receive interval specification register (adti). (a) serial operating mode register 1 (csim1) csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim1 to 00h. 399 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud notes 1. if the external clock input has been selected by clearing csim11 to 0, clear bit 1 (busy 1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. 2. can be used freely as a port function. 3. can be used as p20 (cmos input/output) when only transmission is performed (clear bit 7 (re) of adtc to 0). remark : don t care pm : port mode register p : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection external clock input to sck1 pin note 1 8-bit timer register 2 (tm2) output sck1 (input) 1 clock specified by bits 4 to 7 of timer clock select register 3 (tcl3) csie1 0 csim10 0 1 ff68h 00h r/w address after reset r/w csim11 p20 pm21 p21 pm22 note 3 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function 1 0 1 0 001 1 note 2 note 2 note 2 note 2 count operation si1 (input) operation stop clear p20 (cmos i/o) p22 (cmos i/o) ate 0 serial interface channel 1 operating mode selection 3-wire serial i/o mode dir 0 1 start bit msb lsb si1 pin function si1/p20 (input) so1 pin function so1 (cmos output) pm20 so1/p21 pin function so1 (cmos output) p21 (cmos i/o) sck1 (cmos output) 1 note 2 note 2 note 3 note 3 p22 1 3-wire serial i/o mode with automatic transmit/receive function 400 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (b) automatic data transmit/receive control register (adtc) adtc is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adtc to 00h. notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. the termination of automatic transmission/reception should be judged by using trf, not csiif1 (interrupt request flag). caution when an external clock input is selected by clearing bit 1 (csim11) of serial operating mode register 1 (csim1) to 0, clear strb and busy1 of adtc to 0, 0 (handshake control cannot be executed when an external clock is input). remark : don t care <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff69h 00h r/w note 1 address after reset r/w busy1 0 1 1 busy input control not using busy input busy input enabled (active high) busy input enabled (active low) busy0 0 1 strb 0 1 strobe output control strobe output disabled strobe output enabled trf 1 status of automatic transmit/receive function note 2 detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) during automatic transmission/reception (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection of automatic transmit/receive function no error (this bit is set to 0 when data is written to sio1.) error occurred r/w arld 0 1 operating mode selection of automatic transmit/receive function one-shot mode repetitive one-shot mode r/w re 0 1 receive control of automatic transmit/receive function receive disabled receive enabled r/w erce 0 error check control of automatic transmit/receive function error check disabled error check enabled (only when busy1 = 1) 0 1 401 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (c) automatic data transmit/receive interval specification register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adti to 00h. notes 1. the interval is dependent only on the cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + , maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency f xx 2 6 f xx f sck 28 0.5 f xx f sck 36 1.5 f xx 2 6 data transfer interval specification (f xx = 5.0 mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 18.4 s + 0.5/f sck 31.2 s + 0.5/f sck 44.0 s + 0.5/f sck 56.8 s + 0.5/f sck 69.6 s + 0.5/f sck 82.4 s + 0.5/f sck 95.2 s + 0.5/f sck 108.0 s + 0.5/f sck 120.8 s + 0.5/f sck 133.6 s + 0.5/f sck 146.4 s + 0.5/f sck 159.2 s + 0.5/f sck 172.0 s + 0.5/f sck 184.8 s + 0.5/f sck 197.6 s + 0.5/f sck 210.4 s + 0.5/f sck maximum note 2 20.0 s + 1.5/f sck 32.8 s + 1.5/f sck 45.6 s + 1.5/f sck 58.4 s + 1.5/f sck 71.2 s + 1.5/f sck 84.0 s + 1.5/f sck 96.8 s + 1.5/f sck 109.6 s + 1.5/f sck 122.4 s + 1.5/f sck 135.2 s + 1.5/f sck 148.0 s + 1.5/f sck 160.8 s + 1.5/f sck 173.6 s + 1.5/f sck 186.4 s + 1.5/f sck 199.2 s + 1.5/f sck 212.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 402 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 f xx 2 6 f xx 28 0.5 f xx f sck 36 1.5 f xx f sck data transfer interval specification (f xx = 5.0 mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 223.2 s + 0.5/f sck 236.0 s + 0.5/f sck 248.8 s + 0.5/f sck 261.6 s + 0.5/f sck 274.4 s + 0.5/f sck 287.2 s + 0.5/f sck 300.0 s + 0.5/f sck 312.8 s + 0.5/f sck 325.6 s + 0.5/f sck 338.4 s + 0.5/f sck 351.2 s + 0.5/f sck 364.0 s + 0.5/f sck 376.8 s + 0.5/f sck 389.6 s + 0.5/f sck 402.4 s + 0.5/f sck 415.2 s + 0.5/f sck maximum note 224.8 s + 1.5/f sck 237.6 s + 1.5/f sck 250.4 s + 1.5/f sck 263.2 s + 1.5/f sck 276.0 s + 1.5/f sck 288.8 s + 1.5/f sck 301.6 s + 1.5/f sck 314.4 s + 1.5/f sck 327.2 s + 1.5/f sck 340.0 s + 1.5/f sck 352.8 s + 1.5/f sck 365.6 s + 1.5/f sck 378.4 s + 1.5/f sck 391.2 s + 1.5/f sck 404.0 s + 1.5/f sck 416.8 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 403 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud notes 1. the interval is dependent only on the cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 f xx 2 6 f xx 28 0.5 f xx f sck 36 1.5 f xx f sck data transfer interval specification (f xx = 2.5 mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 36.8 s + 0.5/f sck 62.4 s + 0.5/f sck 88.0 s + 0.5/f sck 113.6 s + 0.5/f sck 139.2 s + 0.5/f sck 164.8 s + 0.5/f sck 190.4 s + 0.5/f sck 216.0 s + 0.5/f sck 241.6 s + 0.5/f sck 267.2 s + 0.5/f sck 292.8 s + 0.5/f sck 318.4 s + 0.5/f sck 344.0 s + 0.5/f sck 369.6 s + 0.5/f sck 395.2 s + 0.5/f sck 420.8 s + 0.5/f sck maximum note 2 40.0 s + 1.5/f sck 65.6 s + 1.5/f sck 91.2 s + 1.5/f sck 116.8 s + 1.5/f sck 142.4 s + 1.5/f sck 168.0 s + 1.5/f sck 193.6 s + 1.5/f sck 219.2 s + 1.5/f sck 244.8 s + 1.5/f sck 270.4 s + 1.5/f sck 296.0 s + 1.5/f sck 321.6 s + 1.5/f sck 347.2 s + 1.5/f sck 372.8 s + 1.5/f sck 398.4 s + 1.5/f sck 424.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adt i note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 404 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expression is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) + + maximum = (n + 1) + + cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling the data transfer interval by means of automatic transmission/ reception using adti, busy control (see 18.4.3 (4) (a) busy control option) is invalid. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f sck : serial clock frequency 2 6 f xx 2 6 f xx 28 0.5 f xx f sck 36 1.5 f xx f sck data transfer interval specification (f xx = 2.5 mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 446.4 s + 0.5/f sck 472.0 s + 0.5/f sck 497.6 s + 0.5/f sck 523.2 s + 0.5/f sck 548.8 s + 0.5/f sck 574.4 s + 0.5/f sck 600.0 s + 0.5/f sck 625.6 s + 0.5/f sck 651.2 s + 0.5/f sck 676.8 s + 0.5/f sck 702.4 s + 0.5/f sck 728.0 s + 0.5/f sck 753.6 s + 0.5/f sck 779.2 s + 0.5/f sck 804.8 s + 0.5/f sck 830.4 s + 0.5/f sck maximum note 449.6 s + 1.5/f sck 475.2 s + 1.5/f sck 500.8 s + 1.5/f sck 526.4 s + 1.5/f sck 552.0 s + 1.5/f sck 577.6 s + 1.5/f sck 603.2 s + 1.5/f sck 628.8 s + 1.5/f sck 654.4 s + 1.5/f sck 680.0 s + 1.5/f sck 705.6 s + 1.5/f sck 731.2 s + 1.5/f sck 756.8 s + 1.5/f sck 782.4 s + 1.5/f sck 808.0 s + 1.5/f sck 833.6 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 405 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fac0h of buffer ram (up to fadfh at maximum). the transmit data should be in order from higher address to lower address. <2> set the value obtained by subtracting 1 from the number of transmit data bytes to the automatic data transmit/receive address pointer (adtp). (b) automatic transmit/receive mode setting <1> set csie1 and ate of serial operating mode register 1 (csim1) to 1. <2> set re of the automatic data transmit/receive control register (adtc) to 1. <3> set a data transmit/receive interval in the automatic data transmit/receive interval specification register (adti). <4> write any value to serial i/o shift register 1 (sio1) (transfer start trigger). caution writing any value to sio1 orders the start of the automatic transmit/receive operation; the written value has no meaning. the following operations are automatically carried out when (a) and (b) are carried out. after the buffer ram data specified by adtp is transferred to sio1, transmission is carried out (start of automatic transmission/reception). the received data is written to the buffer ram address specified by adtp. adtp is decremented and the next data transmission/reception is carried out. data transmission/ reception continues until the adtp decremental output becomes 00h and the data at address fac0h is output (end of automatic transmission/reception). when automatic transmission/reception is terminated, trf is cleared to 0. 406 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (3) communication operation (a) basic transmission/reception mode this transmission/reception mode is the same as the 3-wire serial i/o mode in which the specified number of data are transmitted/received in 8-bit units. serial transfer is started when any data is written to serial i/o shift register 1 (sio1) while bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. when the final byte has been sent, an interrupt request flag (csiif1) is set. however, judge the termination of auto transmit and receive not by csiif1, but by bit 3 (trf) of the automatic data transmit/ receive control register (adtc). if busy control and strobe control are not executed, the p23/stb/txd1 and p24/busy/rxd1 pins can be used as normal i/o ports. figure 18-8 shows the basic transmission/reception mode operation timing, and figure 18-9 shows the operation flowchart. figure 18-10 shows the operation of the internal buffer ram when 6 bytes of data are transmitted or received. figure 18-8. basic transmission/reception mode operation timing cautions 1. because, in the basic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer ram after 1-byte transmission/ reception, an interval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu processing and the value of the automatic data transmit/receive interval specification register (adti) (see (5) automatic data trans- mit/receive interval). 2. when trf is cleared, the so1 pin becomes low level. remark csiif1: interrupt request flag trf: bit 3 of automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval 407 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-9. basic transmission/reception mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 trf: bit 3 of automatic data transmit/receive control register (adtc) start write transmit data in internal buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from internal buffer ram to sio1 transmission/reception operation write receive data from sio1 to internal buffer ram pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution 408 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud in 6-byte transmission/reception (arld = 0, re = 1) in basic transmit/receive mode, the internal buffer ram operates as follows. (i) before transmission/reception (see figure 18-10 (a)) after any data has been written to serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the internal buffer ram to sio1. when transmission of the first byte is completed, receive data 1 (r1) is transferred from sio1 to the buffer ram, and the automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sio1. (ii) 4th byte transmission/reception point (see figure 18-10 (b)) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to sio1. when transmission of the fourth byte is completed, receive data 4 (r4) is transferred from sio1 to the internal buffer ram, and adtp is decremented. (iii) completion of transmission/reception (see figure 18-10 (c)) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sio1 to the internal buffer ram, and the interrupt request flag (csiif1) is set (intcsi1 generation). figure 18-10. internal buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (1/2) (a) before transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 1 (r1) sio1 0 csiif1 5 adtp 1 409 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-10. internal buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (2/2) (b) 4th byte transmission/reception (c) completion of transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 4 (r4) sio1 0 csiif1 2 adtp 1 receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) receive data 4 (r4) receive data 5 (r5) receive data 6 (r6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp 410 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (b) basic transmission mode in this mode, 8-bit unit data is transmitted the specified number of times. serial transfer is started when any data is written to serial i/o shift register 1 (sio1) while bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. when the final byte has been sent, an interrupt request flag (csiif1) is set. however, judge the termination of automatic transmit and receive not by csiif1, but by bit 3 (trf) of the automatic data transmit/receive control register (adtc). if a receive operation, busy control and strobe control are not executed, the p20/si1, p23/stb/txd1 and p24/busy/rxd1 pins can be used as normal i/o ports. figure 18-11 shows the basic transmission mode operation timing, and figure 18-12 shows the operation flowchart. figure 18-13 shows the operation of the internal buffer ram when 6 bytes of data are transmitted or received. figure 18-11. basic transmission mode operation timing cautions 1. because, in the basic transmission mode, the automatic transmit/receive function reads data from the internal buffer ram after 1-byte transmission, an interval is inserted until the next transmission. as buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu process- ing and the value of the automatic data transmit/receive interval specification register (adti) (see (5) automatic data transmit/receive interval). 2. when trf is cleared, the so1 pin becomes low level. remark csiif1: interrupt request flag trf: bit 3 of automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf interval 411 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-12. basic transmission mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 trf: bit 3 of automatic data transmit/receive control register (adtc) start write transmit data in internal buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from internal buffer ram to sio1 transmit operation pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution 412 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud in 6-byte transmission (arld = 0, re = 0) in basic transmit mode, the internal buffer ram operates as follows. (i) before transmission (see figure 18-13 (a).) after any data has been written to serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the internal buffer ram to sio1. when transmission of the first byte is completed, the automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sio1. (ii) 4th byte transmission point (see figure 18-13 (b).) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to sio1. when transmission of the fourth byte is completed, adtp is decremented. (iii) completion of transmission (see figure 18-13 (c).) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is set (intcsi1 generation). figure 18-13. internal buffer ram operation in 6-byte transmission (in basic transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp 1 413 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-13. internal buffer ram operation in 6-byte transmission (in basic transmit mode) (2/2) (b) 4th byte transmission point (c) completion of transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 2 adtp 1 transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp 414 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial transmission is started by writing any data to serial i/o shift register 1 (sio1) when bit 7 (csie1) of serial operating mode register 1 (csim1) is set to 1. unlike the basic transmission mode, after the final byte (data at address fac0h) has been transmitted, the interrupt request flag (csiif1) is not set, the value at the time when transmission was started is set in the automatic data transmit/receive address pointer (adtp) again, and the internal buffer ram contents are transmitted again. when a reception operation, busy control and strobe control are not performed, the p20/si1, p23/stb/ txd1 and p24/busy/rxd1 pins can be used as normal i/o ports. the repeat transmission mode operation timing is shown in figure 18-14, and the operation flowchart in figure 18-15. figure 18-16 shows the operation of the internal buffer ram when 6 bytes of data are transmitted in the repeat transmission mode. figure 18-14. repeat transmission mode operation timing caution because, in the repeat transmission mode, a read is performed on the buffer ram after the transmission of one byte, an interval is inserted in the period up to the next transmission. as buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu operation and the value of the automatic data transmit/receive interval specification register (adti) (see (5) automatic data transmit/receive interval). d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sck1 so1 415 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-15. repeat transmission mode flowchart adtp: automatic data transmit/receive address pointer adti: automatic data transmit/receive interval specification register sio1: serial i/o shift register 1 start write transmit data in internal buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from internal buffer ram to sio1 transmit operation pointer value = 0 no yes decrement pointer value software execution hardware execution reset adtp 416 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud in 6-byte transmission (arld = 1, re = 0) in repeat transmit mode, the internal buffer ram operates as follows. (i) before transmission (see figure 18-16 (a).) after any data has been written to serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the internal buffer ram to sio1. when transmission of the first byte is completed, the automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sio1. (ii) upon completion of transmission of 6 bytes (see figure 18-16 (b).) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is not set. the internal pointer value is reset in adtp. (iii) 7th byte transmission point (see figure 18-16 (c).) transmit data 1 (t1) is transferred from the internal buffer ram to sio1 again. when transmission of the first byte is completed, adtp is decremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sio1. figure 18-16. internal buffer ram operation in 6-byte transmission (in repeat transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp 1 417 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-16. internal buffer ram operation in 6-byte transmission (in repeat transmit mode) (2/2) (b) upon completion of transmission of 6 bytes (c) 7th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 0 adtp transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp 1 418 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (d) automatic transmission/reception suspending and restart automatic transmission/reception can be temporarily suspended by clearing bit 7 (csie1) of serial operating mode register 1 (csim1) to 0. if during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (csie1) is cleared to 0. it is suspended upon completion of 8-bit data transfer. when suspended, bit 3 (trf) of the automatic data transmit/receive control register (adtc) is cleared to 0 after transfer of the 8th bit, and all the port pins used as serial interface alternate-function pins (p20/ si1, p21/so1, p22/sck1, p23/stb/txd1 and p24/busy/rxd1) are set to the port mode. to restart automatic transmission/reception, set csie1 to 1 and write the desired value to serial i/o shift register 1 (sio1). the remaining data can be transmitted in this way. cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set, even if 8-bit data transfer is in progress. when the halt mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. when suspending automatic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while trf = 1. figure 18-17. automatic transmission/reception suspension and restart csie1: bit 7 of serial operating mode register 1 (csim1) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command csie1 = 1, write to sio1 suspend csie1 = 0 (suspended command) 419 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (4) synchronization control busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. by using these functions, a shift in bits being transmitted or received can be detected. (a) busy control option busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. when using this busy control option, the following conditions must be satisfied. bit 5 (ate) of serial operating mode register 1 (csim1) is set to 1. bit 1 (busy1) of the automatic data transmit/receive control register (adtc) is set to 1. figure 18-18 shows the system configuration of the master device and a slave device when the busy control option is used. figure 18-18. system configuration when busy control option is used sck1 so1 si1 sck1 so1 si1 busy master device ( pd780058, 780058y subseries) slave device the master device inputs the busy signal output by the slave device to the busy/p24 pin. the master device samples the input busy signal in synchronization with the falling edge of the serial clock. even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. if the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission/reception of the 8-bit data, the busy input becomes valid. after that, the master transmission/reception is kept waiting while the busy signal is active. the active level of the busy signal is set by bit 0 (busy0) of adtc. busy0 = 0: active high busy0 = 1: active low when using the busy control option, select the internal clock as the serial clock. control with the busy signal cannot be implemented with an external clock. figure 18-19 shows the operation timing when the busy control option is used. caution busy control cannot be used simultaneously with the interval time control function of the automatic data transmit/receive interval specification register (adti). if used, busy control is invalid. 420 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-19. operation timing when busy control option is used (when busy0 = 0) sck1 d7 so1 si1 csiif1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy trf clears busy input busy input is valid wait caution if trf is cleared, the so1 pin goes low. remark csiif1: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) when the busy signal becomes inactive, waiting is released. if the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next clock. because the busy signal is asynchronous to the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. it takes 0.5 clock until data transfer is started after the busy signal was sampled. to accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clocks. figure 18-20 shows the timing of the busy signal and wait release. this figure shows an example where the busy signal is active as soon as transmission/reception has been started. 421 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-20. busy signal and wait release (when busy0 = 0) (b) busy & strobe control option strobe control is a function to synchronize data transmission/reception between the master and slave devices. the master device outputs the strobe signal from the stb/p23 pin when 8-bit transmission/ reception has been completed. by this signal, the slave device can determine the timing of the end of data transmission. therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. to use the strobe control option, the following conditions must be satisfied. bit 5 (ate) of serial operating mode register 1 (csim1) is set to 1. bit 2 (strb) of the automatic data transmit/receive control register (adtc) is set to 1. usually, the busy control and strobe control options are simultaneously used as handshake signals. in this case, the strobe signal is output from the stb/p23 pin, the busy/p24 pin is sampled, and transmission/reception can be kept waiting while the busy signal is input. when the strobe control option is not used, the p23/stb pin can be used as a normal i/o port pin. figure 18-21 shows the operation timing when the busy & strobe control options are used. when the strobe control option is used, the interrupt request flag (csiif1) that is set on completion of transmission/reception is set after the strobe signal is output. sck1 d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy (active high) 1.5 clocks (min.) busy input released busy input valid wait if made inactive immediately after sampled 422 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud figure 18-21. operation timing when busy & strobe control options are used (when busy0 = 0) stb sck1 d7 so1 si1 csiif1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy trf busy input released busy input valid caution when trf is cleared, the so1 pin goes low. remark csiif1: interrupt request flag trf: bit 3 of the automatic data transmit/receive control register (adtc) 423 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (c) bit shift detection by busy signal during automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. in this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. a bit shift is detected by using the busy signal as follows. the slave outputs the busy signal after the rising of the eighth serial clock during data transmission/ reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). the master samples the busy signal in synchronization with the falling edge of the leading side of the serial clock. if a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. if the sampled serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by setting bit 4 (err) of the automatic data transmit/receive control register (adtc) to 1). figure 18-22 shows the operation timing of the bit shift detection function by the busy signal. figure 18-22. operation timing of bit shift detection function by busy signal (when busy0 = 1) sck1 (slave) d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy csiif1 csie1 err d7 d7 busy not detected error interrupt request generated error detected bit shift due to noise sck1 (master) csiif1: interrupt request flag csie1: bit 7 of serial operating mode register 1 (csim1) err: bit 4 of the automatic data transmit/receive control register (adtc) 424 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (5) automatic transmit/receive interval time when using the automatic transmit/receive function, the read/write operations from/to the internal buffer ram are performed after transmitting/receiving one byte. therefore, an interval is inserted before the next transmit/ receive operation. since the read/write operations from/to the buffer ram are performed in parallel with the cpu processing when using the automatic transmit/receive function with the internal clock, the interval depends on the value which is set in the automatic transmit/receive interval specification register (adti) and the cpu processing at the rising edge of the eighth serial clock. whether it depends on the adti or not can be selected by setting bit 7 of adti (adti7). when it is cleared to 0, the interval depends only on the cpu processing. when it is set to 1, the interval depends on the contents of adti or the cpu processing, whichever is greater. when the automatic transmit/receive function is used with an external clock, it must be selected so that the interval may be longer than the value indicated by paragraph (b). figure 18-23. automatic data transmit/receive interval time csiif1: interrupt request flag sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval 425 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (a) when the automatic transmit/receive function is used with the internal clock if bit 1 (csim11) of serial operating mode register 1 (csim1) is set to 1, the internal clock operates. if the automatic transmit/receive function is operated with the internal clock, the interval timing according to cpu processing is as follows. when bit 7 (adti7) of the automatic data transmit/receive interval specification register (adti) is cleared to 0, the interval depends on the cpu processing. when adti7 is set to 1, it depends on the contents of adti or the cpu processing, whichever is greater. see figure 18-5 automatic data transmit/receive interval specification register format for the intervals set by adti. table 18-2. interval timing according to cpu processing (when internal clock is operating) cpu processing interval time when using multiplication instruction max. (2.5t sck , 13t cpu ) when using division instruction max. (2.5t sck , 20t cpu ) external access 1 wait mode max. (2.5t sck , 9t cpu ) other than above max. (2.5t sck , 7t cpu ) t sck :1/f sck f sck : serial clock frequency t cpu : 1/f cpu f cpu : cpu clock (set by bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) and bit 0 (mcs) of the oscillation mode select register (osms)) max. (a, b): a or b, whichever is greater figure 18-24. operation timing with automatic data transmit/receive function performed using internal clock f x : main system clock oscillation frequency f cpu : cpu clock (set by bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc)) t cpu : 1/f cpu t sck :1/f sck f sck : serial clock frequency f x f cpu sck1 so1 si1 t cpu t sck d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval 426 chapter 18 serial interface channel 1 user's manual u12013ej3v2ud (b) when using automatic transmit/receive function with external clock an external clock is used when bit 1 (csim11) of serial operating mode register 1 (csim1) is cleared to 0. to use the automatic transmit/receive function with an external clock, the external clock must be input so that the interval time is as follows. table 18-3. interval time according to cpu processing (with external clock) cpu processing interval time when using multiplication instruction 13t cpu or more when using division instruction 20t cpu or more external access 1 wait mode 9t cpu or more other than above 7t cpu or more t cpu : 1/f cpu f cpu : cpu clock (set by the bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) and bit 0 (mcs) of the oscillation mode select register (osms)) 427 user's manual u12013ej3v2ud chapter 19 serial interface channel 2 19.1 functions of serial interface channel 2 serial interface channel 2 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode (with time-division transfer function) ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) asynchronous serial interface (uart) mode (with time-division transfer function) in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by dividing the clock input to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. two sets of data i/o pins (rxd and txd) are provided, and the pin to be used can be selected by software (time-division transfer function). however, only one set of pins can be used at one time. cautions 1. if it is not necessary to change the data i/o pin, use of the rxd0/si2/p70 and txd0/so2/ p71 pins is recommended. if only port 2 (rxd1/busy/p24 and txd1/stb/p23) is used as data i/o pins, the function of port 7 is limited. 2. when using the busy control option or busy & strobe control option in the 3-wire serial i/o mode with automatic transmit/receive function of serial interface channel 1, the rxd1/ busy/p24 and txd1/stb/p23 pins cannot be used as data i/o pins. (3) 3-wire serial i/o mode (msb-first/lsb-first switchable) in this mode, 8-bit data transfer is performed using three lines: the serial clock (sck2), and serial data lines (si2, so2). in the 3-wire serial i/o mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed. either the msb or lsb can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. the 3-wire serial i/o mode is useful for connection to peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75x/xl series, 78k series, 17k series, etc. 428 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.2 configuration of serial interface channel 2 serial interface channel 2 consists of the following hardware. table 19-1. configuration of serial interface channel 2 item configuration registers transmit shift register (txs) receive shift register (rxs) receive buffer register (rxb) control registers serial operating mode register 2 (csim2) asynchronous serial interface mode register (asim) asynchronous serial interface status register (asis) baud rate generator control register (brgc) serial interface pin select register (sips) 429 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud figure 19-1. block diagram of serial interface channel 2 note see figure 19-2 for the baud rate generator configuration. internal bus asynchronous serial interface mode register asynchronous serial interface status register receive buffer register (rxb/sio2) direction controller receive shift register (rxs) reception controller intsr/intcsi2 csie2 csim 22 csck intser sck output controller baud rate generator f xx to f xx /2 10 internal bus csck sck intst baud rate generator control register note serial operating mode register 2 pe fe ove transmission controller isrm asck/ sck2/p72 pm72 direction controller transmit shift register (txs/sio2) rxe ps1 ps0 cl sl isrm txe sck 4 4 csie2 txe rxe mdl3 mdl2 mdl1 mdl0 tps3 tps2 tps1 tps0 txd0/so2/p71 pm71 txd1/stb/p23 pm23 selector selector rxd0/si2/p70 rxd1/busy/p24 sips21 sips20 serial interface pin select register 430 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud figure 19-2. baud rate generator block diagram tps3 tps2 tps1 tps0 internal bus mdl3 mdl2 mdl1 mdl0 baud rate generator control register 4 txe csie2 5-bit counter selector selector decoder 1/2 selector transmit clock 1/2 selector receive clock match match mdl0 to mdl3 5-bit counter rxe start bit detection selector f xx to f xx /2 10 tps0 to tps3 sck csck asck/sck2/p72 4 4 start bit sampling clock 431 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (1) transmit shift register (txs) this register is used to set the transmit data. the data written in txs is transmitted as serial data. if the data length is specified as 7 bits, bits 0 to 6 of the data written in txs are transferred as transmit data. writing data to txs starts the transmit operation. txs is written with an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs to ffh. caution txs must not be written during a transmit operation. txs and the receive buffer register (rxb) are allocated to the same address, and when a read is performed, the value of rxb is read. (2) receive shift register (rxs) this register is used to convert serial data input to the rxd0 (rxd1) pin into parallel data. when one byte of data is received, the receive data is transferred to the receive buffer register (rxb). rxs cannot be directly manipulated by a program. (3) receive buffer register (rxb) this register holds receive data. each time one byte of data is received, new receive data is transferred from the receive shift register (rxs). if the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of rxb, and the msb of rxb is always cleared to 0. rxb is read with an 8-bit memory manipulation instruction. it cannot be written to. reset input sets rxb to ffh. caution rxb and the transmit shift register (txs) are allocated to the same address, and when a write is performed, the value is written to txs. (4) transmission controller this circuit performs transmit operation control such as the addition of a start bit, parity bit, and stop bit to data written in the transmit shift register (txs) in accordance with the contents set in the asynchronous serial interface mode register (asim). (5) reception controller this circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (asim). it performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (asis) in accordance with the error contents. 432 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.3 control registers of serial interface channel 2 serial interface channel 2 is controlled by the following five registers. ? serial operating mode register 2 (csim2) ? asynchronous serial interface mode register (asim) ? asynchronous serial interface status register (asis) ? baud rate generator control register (brgc) ? serial interface pin select register (sips) (1) serial operating mode register 2 (csim2) this register is set when serial interface channel 2 is used in the 3-wire serial i/o mode. csim2 is set with a 1-bit or an 8-bit memory manipulation instruction. reset input sets csim2 to 00h. figure 19-3. format of serial operating mode register 2 cautions 1. be sure to clear bits 0 and 3 to 6 to 0. 2. when uart mode is selected, csim2 should be cleared to 00h. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 ff72h 00h r/w address after reset r/w csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled 433 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an i/o port. cautions 1. when the 3-wire serial i/o mode is selected, asim should be cleared to 00h. 2. the serial transmit/receive operation must be stopped before changing the operating mode. (2) asynchronous serial interface mode register (asim) this register is set when serial interface channel 2 is used in the asynchronous serial interface mode. asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim to 00h. figure 19-4. format of asynchronous serial interface mode register <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt request in case of error occurrence reception completion interrupt request generated in case of error occurrence reception completion interrupt request not generated in case of error occurrence sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission. no parity test in reception (parity error not generated). 0 1 1 odd parity 0 434 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud table 19-2. operating mode settings of serial interface channel 2 (1/2) (1) operation stop mode (2) 3-wire serial i/o mode notes 1. can be used freely as a port function. 2. can be used as p70 (cmos i/o) when only transmission is performed. remark : don t care pm : port mode register p : port output latch p72/sck2 /asck pin function p71/so2/ txd0 pin function p70/si2/ rxd0 pin function shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 0 0 0 note 1 pm23 p23 pm24 p24 p70 p71 p23/stb/ txd1 pin function p23/stb p24/busy/ rxd1 pin function p24/busy p72 other than above setting prohibited sips sips21 sips20 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 p72/sck2 /asck pin function p71/so2/ txd0 pin function p70/si2/ rxd0 pin function shift clock start bit txe rxe sck csie2 csim22 csck asim csim2 0 00 1 1 0 1 0 1 0 1 note 2 note 2 0 1 note 1 note 1 note 1 note 1 1 0 1 0 1 1 msb lsb external clock internal clock external clock internal clock si2 si2 so2 (cmos output) so2 (cmos output) p23/stb/ txd1 pin function p23/stb p24/busy/ rxd1 pin function p24/busy sck2 input sck2 output sck2 input sck2 output other than above setting prohibited sips sips21 sips20 note 2 note 2 pm70 p70 pm71 p71 pm72 p72 pm23 p23 pm24 p24 435 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud table 19-2. operating mode setting of serial interface channel 2 (2/2) (3) asynchronous serial interface mode notes 1. can be used freely as a port function. 2. the set value differs between when the actual device operates and when emulation is executed by the in-circuit emulator. for details, see 19.4.5 restrictions in uart mode 2 . remark : don t care pm : port mode register p : port output latch p72/sck2 /asck pin function p71/so2/ txd0 pin function p70/si2/ rxd0 pin function shift clock start bit txe rxe sck csie2 csim22 csck asim csim2 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 note 1 note 1 0 0 0 0 1 1 1 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 1 note 1 note 1 note 1 note 1 note 1 1 1 1 1 1 1 lsb external clock internal clock external clock internal clock external clock internal clock external clock internal clock external clock internal clock external clock internal clock p70 rxd0 p70 p70 (input) p70 (input) txd0 (cmos output) p71 txd0 (cmos output) high output p71 high output p23/stb/ txd1 pin function p23/stb txd1 p23/stb txd1 p24/busy/ rxd1 pin function p24/busy p24/busy rxd1 rxd1 asck input p72 asck input p72 asck input p72 asck input p72 asck input p72 asck input p72 other than above setting prohibited sips sips21 sips20 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 note 2 note 2 0 0 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 1 pm70 p70 pm71 p71 pm72 p72 pm23 p23 pm24 p24 436 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud notes 1. the receive buffer register (rxb) must be read when an overrun error occurs. overrun errors will continue to occur until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register (asim), only single stop bit detection is performed during reception. (3) asynchronous serial interface status register (asis) this is a register which displays the type of error when a reception error occurs in the asynchronous serial interface mode. asis is read with a 1-bit or 8-bit memory manipulation instruction. in 3-wire serial i/o mode, the contents of asis are undefined. reset input clears asis to 00h. figure 19-5. format of asynchronous serial interface status register pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error did not occur overrun error occurred note 1 (when next receive operation is completed before data is read from receive buffer register) fe 0 1 framing error flag framing error did not occur framing error occurred note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error did not occur parity error occurred (when transmit data parity does not match) 437 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (4) baud rate generator control register (brgc) this register sets the serial clock for serial interface channel 2. brgc is set with an 8-bit memory manipulation instruction. reset input clears brgc to 00h. figure 19-6. format of baud rate generator control register (1/2) note can only be used in 3-wire serial i/o mode. remarks 1. f sck : 5-bit counter source clock 2. k: value set in mdl0 to mdl3 (0 k 14) baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck note 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k 438 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud figure 19-6. format of baud rate generator control register (2/2) tps3 tps2 tps1 tps0 5-bit counter source clock selection n mcs = 1 mcs = 0 0000f xx /2 10 f xx /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when brgc is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs: bit 0 of the oscillation mode select register (osms) 4. n: value set in tps0 to tps3 (1 n 11) 5. values in parentheses apply to operation with f x = 5.0 mhz 439 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud the baud rate transmit/receive clock generated is either a signal divided from the main system clock, or a signal divided from the clock input from the asck pin. (a) generation of baud rate transmit/receive clock from main system clock the transmit/receive clock is generated by dividing the main system clock. the baud rate generated from the main system clock is obtained from the following expression. [baud rate] = [hz] where, f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n: value set in tps0 to tps3 (1 n 11) k: value set in mdl0 to mdl3 (0 k 14) table 19-3. relationship between main system clock and baud rate f x = 5.0 mhz f x = 4.19 mhz mcs = 1 mcs = 0 mcs = 1 mcs = 0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 C 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C 2.01 e3h C 2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1,200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2,400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4,800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9,600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19,200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31,250 74h 0 64h 0 71h C 1.31 61h C 1.31 38,400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76,800 60h 1.73 50h 1.73 5bh 1.14 remark mcs: bit 0 of the oscillation mode select register (osms) f xx 2 n (k + 16) baud rate (bps) 440 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (b) generation of baud rate transmit/receive clock from external clock input from asck pin the transmit/receive clock is generated by dividing the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained from the following expression. [baud rate] = [hz] f asck : frequency of clock input to asck pin k: value set in mdl0 to mdl3 (0 k 14) table 19-4. relationship between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1,200 38.4 khz 2,400 76.8 khz 4,800 153.6 khz 9,600 307.2 khz 19,200 614.4 khz 31,250 1,000.0 khz 38,400 1,228.8 khz f asck 2 (k + 16) 441 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (5) serial interface pin select register (sips) this register selects the input/output pins when serial interface channel 2 is used in the asynchronous serial interface mode (with time-division transfer function). sips is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sips to 00h. to select the input/output pins, the port mode register and the output latch of the port must be set. for details, see table 19-2 operating mode settings of serial interface channel 2. figure 19-7. format of serial interface pin select register cautions 1. select the input/output pins after stopping serial transmission/reception. 2. when using the busy control option or busy & strobe control option in the 3-wire serial i/o mode with automatic transmit/receive function of serial interface channel 1, the rxd1/ busy/p24 and txd1/stb/p23 pins cannot be used as data i/o pins. 3. sips21 is valid only when the txe flag is ??and sips20 is valid only when the rxe flag is ?? 4. there are restrictions when sips21 = 1 (when the txd1 pin is used as an output pin for uart transmission). for details, see 19.4.5 restrictions in uart mode 2. 6543210 7 symbol sips 0 0 sips21 sips20 0000 ff75h 00h r/w address after reset r/w sips21 0 1 selection input/output pin of asynchronous serial interface input pin: rxd0/si2/p70 output pin: txd0/so2/p71 input pin: rxd1/busy/p24 output pin: txd1/stb/p23 sips20 0 1 input pin: rxd1/busy/p24 output pin: txd0/so2/p71 0 1 1 input pin: rxd0/si2/p70 output pin: txd1/stb/p23 0 442 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.4 operation of serial interface channel 2 the following three operating modes are available for serial interface channel 2. ? operation stop mode ? asynchronous serial interface (uart) mode (with time-division transfer function) ? 3-wire serial i/o mode 19.4.1 operation stop mode in the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. in the operation stop mode, the p70/si2/rxd0, p71/so2/txd0, and p72/sck2/asck pins can be used as normal i/o ports and the p23/stb/txd1, p24/busy/rxd1 pins can be used as normal i/o ports or as the strobe output and busy input for serial interface automatic transmit/receive. (1) register setting operation stop mode is set by serial operating mode register 2 (csim2) and the asynchronous serial interface mode register (asim). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim2 to 00h. caution be sure to clear bits 0 and 3 to 6 to 0. csim 22 6543210 <7> symbol csim2 csie2 0 0 0 0 csck 0 ff72h 00h r/w address after reset r/w csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled 443 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim to 00h. sl <6>543210 <7> symbol asim txe rxe ps1 ps0 cl isrm sck ff70h 00h r/w address after reset r/w rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled 444 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.4.2 asynchronous serial interface (uart) mode (with time-division transfer function) in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by dividing the clock input to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. two sets of data i/o pins (rxd and txd) are provided, and the pin to be used can be selected by software (time- division transfer function). however, only one set of pins can be used at one time. cautions 1. if it is not necessary to change the data i/o pin, use of the rxd0/si2/p70 and txd0/so2/p71 pins is recommended. if only port 2 (rxd1/busy/p24 and txd1/stb/p23) is used as data i/o pins, the function of port 7 is limited. 2. when using the busy control option or busy & strobe control option in the 3-wire serial i/o mode with automatic transmit/receive function of serial interface channel 1, the rxd1/busy/ p24 and txd1/stb/p23 pins cannot be used as data i/o pins. (1) register setting uart mode (with time-division transfer function) is set by serial operating mode register 2 (csim2), the asynchronous serial interface mode register (asim), the asynchronous serial interface status register (asis), the baud rate generator control register (brgc), and the serial interface pin select register (sips). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim2 to 00h. when the uart mode is selected, csim2 should be cleared to 00h. caution be sure to clear bits 0 and 3 to 6 to 0. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w 445 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an i/o port. caution the serial transmit/receive operation must be stopped before changing the operating mode. (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim to 00h. <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt request in case of error occurrence reception completion interrupt request generated in case of error occurrence reception completion interrupt request not generated in case of error occurrence sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission. no parity test in reception (parity error not generated). 0 1 1 odd parity 0 446 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (c) asynchronous serial interface status register (asis) asis is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis to 00h. notes 1. the receive buffer register (rxb) must be read when an overrun error occurs. overrun errors will continue to occur until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register (asim), only single stop bit detection is performed during reception. pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error did not occur overrun error occurred note 1 (when next receive operation is completed before data from receive buffer register is read) fe 0 1 framing error flag framing error did not occur framing error occurred note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error did not occur parity error occurred (when transmit data parity does not match) 447 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (d) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input clears brgc to 00h. remark f sck : 5-bit counter source clock k: value set in mdl0 to mdl3 (0 k 14) (cont d) baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k 448 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud tps3 tps2 tps1 tps0 5-bit counter source clock selection n mcs = 1 mcs = 0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when brgc is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs: bit 0 of the oscillation mode select register (osms) 4. n: value set in tps0 to tps3 (1 n 11) 5. values in parentheses apply to operation with f x = 5.0 mhz. 449 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud the baud rate transmit/receive clock generated is either a signal divided from the main system clock, or a signal divided from the clock input from the asck pin. (i) generation of baud rate transmit/receive clock from main system clock the transmit/receive clock is generated by dividing the main system clock. the baud rate generated from the main system clock is obtained from the following expression. [baud rate] = [hz] where, f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n: value set in tps0 to tps3 (1 n 11) k: value set in mdl0 to mdl3 (0 k 14) table 19-5. relationship between main system clock and baud rate f x = 5.0 mhz f x = 4.19 mhz mcs = 1 mcs = 0 mcs = 1 mcs = 0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 C 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C 2.01 e3h C 2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1,200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2,400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4,800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9,600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19,200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31,250 74h 0 64h 0 71h C 1.31 61h C 1.31 38,400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76,800 60h 1.73 50h 1.73 5bh 1.14 remark mcs: bit 0 of the oscillation mode select register (osms) f xx 2 n (k + 16) baud rate (bps) 450 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (ii) generation of baud rate transmit/receive clock from external clock input from asck pin the transmit/receive clock is generated by dividing the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained from the following expression. [baud rate] = [hz] where, f asck : frequency of clock input to asck pin k: value set in mdl0 to mdl3 (0 k 14) table 19-6. relationship between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1,200 38.4 khz 2,400 76.8 khz 4,800 153.6 khz 9,600 307.2 khz 19,200 614.4 khz 31,250 1,000.0 khz 38,400 1,228.8 khz 2 (k + 16) f asck 451 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (e) serial interface pin select register (sips) sips is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sips to 00h. to select the input/output pins, the port mode register and the output latch of the port must be set. for details, see table 19-2 operating mode settings of serial interface channel 2 . cautions 1. select the input/output pins after stopping serial transmission/reception. 2. when using the busy control option or busy & strobe control option in the 3-wire serial i/o mode with automatic transmit/receive function of serial interface channel 1, the rxd1/ busy/p24 and txd1/stb/p23 pins cannot be used as data i/o pins. 3. sips21 is valid only when the txe flag is 1 and sips20 is valid only when the rxe flag is 1 . 4. there are restrictions when sips21 = 1 (when the txd1 pin is used as an output pin for uart transmission). for details, see 19.4.5 restrictions in uart mode 2. 6543210 7 symbol sips 0 0 sips21 sips20 0000 ff75h 00h r/w address after reset r/w sips21 0 1 selection of input/output pin of asynchronous serial interface input pin: rxd0/si2/p70 output pin: txd0/so2/p71 input pin: rxd1/busy/p24 output pin: txd1/stb/p23 sips20 0 1 input pin: rxd1/busy/p24 output pin: txd0/so2/p71 0 1 1 input pin: rxd0/si2/p70 output pin: txd1/stb/p23 0 452 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (2) communication operation (a) data format the transmit/receive data format is as shown in figure 19-8. figure 19-8. format of asynchronous serial interface transmit/receive data one data frame consists of the following bits: ? start bits .................. 1 bit ? character bits ......... 7 bits/8 bits ? parity bits ................ even parity/odd parity/0 parity/no parity ? stop bits .................. 1 bit/2 bits the specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out by the asynchronous serial interface mode register (asim). when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always 0 . the serial transfer rate is selected by means of asim and the baud rate generator control register (brgc). if a serial data receive error occurs, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (asis). d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame character bit 453 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a 1-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity transmission the number of bits with a value of 1 , including the parity bit, in the transmit data is controlled to be even. the value of the parity bit is as follows: number of bits with a value of 1 in transmit data is odd: 1 number of bits with a value of 1 in transmit data is even: 0 reception the number of bits with a value of 1 , including the parity bit, in the receive data is counted. if it is odd, a parity error occurs. (ii) odd parity transmission conversely to the situation with even parity, the number of bits with a value of 1 , including the parity bit, in the transmit data is controlled to be odd. the value of the parity bit is as follows: number of bits with a value of 1 in transmit data is odd: 0 number of bits with a value of 1 in transmit data is even: 1 reception the number of bits with a value of 1 , including the parity bit, in the receive data is counted. if it is even, a parity error occurs. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error does not occur, irrespective of whether the parity bit is set to 0 or 1 . (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error does not occur. 454 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (c) transmission a transmit operation is started by writing transmit data to the transmit shift register (txs). the start bit, parity bit and stop bit(s) are added automatically. when the transmit operation starts, the data in the transmit shift register (txs) is shifted out, and when the transmit shift register (txs) is empty, a transmission completion interrupt request (intst) is generated. figure 19-9. asynchronous serial interface transmission completion interrupt request generation timing (a) stop bit length: 1 (b) stop bit length: 2 caution rewriting the asynchronous serial interface mode register (asim) should not be per- formed during a transmit operation. if rewriting the asim is performed during transmis- sion, subsequent transmit operations may not be possible (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request (intst) or the interrupt request flag (stif) set by intst. d1 d2 d6 d7 parity d0 txd0 (txd1) (output) intst stop start d1 d2 d6 d7 parity d0 txd0 (txd1) (output) intst stop start 455 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (d) reception when the rxe bit of the asynchronous serial interface mode register (asim) is set to 1, a receive operation is enabled and sampling of the rxd0 (rxd1) pin input is started. rxd0 (rxd1) pin input sampling is performed using the serial clock specified by asim. when the rxd0 (rxd1) pin input becomes low, the 5-bit counter of the baud rate generator (see figure 19-2 ) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. if the rxd0 (rxd1) pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (rxb), and a reception completion interrupt request (intsr) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb. if bit 1 (isrm) of asim is cleared to 0 on occurrence of the error, intsr is generated. if the rxe bit is reset to 0 during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb and the asynchronous serial interface status register (asis) are not changed, and intsr and intser are not generated. figure 19-10. asynchronous serial interface reception completion interrupt request generation timing caution the receive buffer register (rxb) must be read even if a receive error occurs. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. d1 d2 d6 d7 parity d0 rxd0 (rxd1) (input) intsr stop start 456 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (e) receive errors three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. the data reception result error flag is set in the asynchronous serial interface status register (asis) and a receive error interrupt request (intser) is generated. the receive error interrupt is generated faster than receive completion interrupt (intsr). receive error causes are shown in table 19-7. it is possible to determine what kind of error occurred during reception by reading the contents of asis in the reception error interrupt servicing (see figures 19-10 and 19-11 ). the contents of asis are reset to 0 by reading the receive buffer register (rxb) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 19-7. receive error causes receive errors cause parity error transmission-time parity specification and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed before data is read from receive register buffer figure 19-11. receive error timing note intsr is not generated if a receive error occurs while bit 1 (isrm) of the asynchronous serial interface mode register (asim) is set to 1. cautions 1. the contents of the asynchronous serial interface status register (asis) are reset to 0 by reading the receive buffer register (rxb) or receiving the next data. to ascertain the error contents, asis must be read before reading rxb. 2. the receive buffer register (rxb) must be read even if a receive error occurs. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. parity stop d7 d6 d2 d1 d0 r x d (input) intsr note intser (when framing/ overrun error occurs) intser (when parity error occurs) start 457 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (3) uart mode cautions (a) when the transmission under execution has been stopped by clearing bit 7 (txe) of the asynchronous serial interface mode register (asim) to 0, be sure to set the transmit shift register (txs) to ffh, then set txe to 1 before executing the next transmission. (b) when the reception under execution has been stopped by clearing bit 6 (rxe) of the asynchronous serial interface mode register (asim) to 0, the status of the receive buffer register (rxb) and whether the receive completion interrupt request (intsr) is generated differ depending on the timing at which reception is stopped. figure 19-12 shows the timing. figure 19-12. status of receive buffer register (rxb) and generation of interrupt request (intsr) when reception is stopped when rxe is cleared to 0 at the time indicated by <1> , rxb holds the previous data and does not generate intsr. when rxe is cleared to 0 at the time indicated by <2> , rxb renews the data and does not generate intsr. when rxe is cleared to 0 at the time indicated by <3> , rxb renews the data and generates intsr. parity rxd0 (rxd1) pin rxb intsr <3> <1> <2> 458 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75x/xl series, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck2), serial output (so2), and serial input (si2). in the 3-wire serial i/o mode, the p23/stb/txd1, p24/busy/rxd1 pins can be used as normal i/o ports. (1) register setting 3-wire serial i/o mode is set by serial operating mode register 2 (csim2), the asynchronous serial interface mode register (asim), and the baud rate generator control register (brgc). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim2 to 00h. caution be sure to clear bits 0 and 3 to 6 to 0. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w 459 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim to 00h. when the 3-wire serial i/o mode is selected, asim should be cleared to 00h. <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output isrm 0 1 control of reception completion interrupt request in case of error occurrence reception completion interrupt request generated in case of error occurrence reception completion interrupt request not generated in case of error occurrence sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission. no parity test in reception (parity error not generated). 0 1 1 odd parity 0 460 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (c) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input clears brgc to 00h. (cont d) remark f sck : 5-bit counter source clock k: value set in mdl0 to mdl3 (0 k 14) baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k 461 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud tps3 tps2 tps1 tps0 5-bit counter source clock selection n mcs = 1 mcs = 0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when brgc is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs: bit 0 of the oscillation mode select register (osms) 4. n: value set in tps0 to tps3 (1 n 11) 5. values in parentheses apply to operation with f x = 5.0 mhz. 462 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud when the internal clock is used as the serial clock in the 3-wire serial i/o mode, set brgc as described below. brgc setting is not required if an external serial clock is used. (i) when the baud rate generator is not used: select the serial clock frequency using tps0 to tps3. be sure then to set mdl0 to mdl3 to 1,1,1,1. the serial clock frequency becomes the same as the source clock frequency for the 5-bit counter. (ii) when the baud rate generator is used: select the serial clock frequency using tps0 to tps3. be sure then to set mdl0 to mdl3 to 1,1,1,1. the serial clock frequency is calculated by the following formula: serial clock frequency = [hz] remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. n: value set in tps0 to tps3 (1 n 11) 4. k: value set in mdl0 to mdl3 (0 k 14) f xx 2 n (k + 16) 463 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud (2) communication operation in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit-wise synchronization with the serial clock. transmit shift register (txs/sio2) and receive shift register (rxs) shift operations are performed in synchronization with the fall of the serial clock sck2. then transmit data is held in the so2 latch and output from the so2 pin. also, receive data input to the si2 pin is latched in the receive buffer register (rxb/sio2) on the rise of sck2. at the end of an 8-bit transfer, the operation of txs/sio2 or rxs stops automatically, and the interrupt request flag (srif) is set. figure 19-13. 3-wire serial i/o mode timing (3) msb/lsb switching as the start bit in the 3-wire serial i/o mode, it is possible to select transfer to start from the msb or lsb. figure 19-14 shows the configuration of the transmit shift register (txs/sio2) and internal bus. as shown in the figure, the msb/lsb can be read or written in reverse form. msb/lsb switching as the start bit can be specified by bit 2 (csim22) of serial operating mode register 2 (csim2). si2 sck2 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so2 do7 do6 do5 do4 do3 do2 do1 do0 srif transfer start at the falling edge of sck2 end of transfer 464 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud figure 19-14. circuit for switching transfer bit order start bit switching is realized by switching the bit order for data write to sio2. the sio2 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to the transmission shift register (txs/sio2) when the following two conditions are satisfied. ? serial interface channel 2 operation control bit (csie2) = 1 ? internal serial clock is stopped or sck2 is a high level after 8-bit serial transfer. caution if csie2 is set to 1 after data write to txs/sio2, transfer does not start. remark csie2: bit 7 of serial operating mode register 2 (csim2) upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (srif) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si2 transmit shift register (txs/sio2) read/write gate so2 sck2 dq so2 latch 465 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.4.4 restrictions in uart mode 1 in the uart mode, the reception completion interrupt request (intsr) is generated a certain time after the reception error interrupt (intser) is generated and then cleared. consequently, the following phenomenon may occur. description if bit 1 (isrm) of the asynchronous serial interface mode register (asim) is set to 1, the reception completion interrupt request (intsr) is not generated on occurrence of a reception error. if the receive buffer register (rxb) is read at certain timing ( a in figure 19-15) during the reception error interrupt (intser) servicing, the internal error flag is cleared to 0. as a result, it is judged that no reception error has occurred, and intsr, which should not be generated, is generated. figure 19-15 illustrates this operation. figure 19-15. reception completion interrupt request generation timing (when isrm = 1) remark isrm: bit 1 of the asynchronous serial interface mode register (asim) f sck : source clock of 5-bit counter of baud rate generator rxb: receive buffer register to avoid this phenomenon, take the following measures. preventive measures in case of framing error or overrun error disable the receive buffer register (rxb) from being read for a certain period (t2 in figure 19-16) after the reception error interrupt request (intser) has been generated. in case of parity error disable the receive buffer register (rxb) from being read for a certain period (t1 + t2 in figure 19-16) after the reception error interrupt request (intser) has been generated. f sck intser (when framing/ overrun error occurs) error flag (internal flag) intsr cleared on reading rxb a interrupt processing routine of cpu reading rxb it is judged that reception error has not occurred, and intsr is generated 466 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud figure 19-16. receive buffer register read disable period t1: time of one data of baud rate selected by baud rate generator control register (brgc) (1/baud rate) t2: time of 2 clocks of source clock (f sck ) of 5-bit counter selected by brgc example of preventive measures here is an example of the above preventive measures. [conditions] f x = 5.0 mhz processor clock control register (pcc) = 00h oscillation mode select register (osms) = 01h baud rate generator control register (brgc) = b0h (2,400 bps selected as baud rate) t cy = 0.4 s (t cy = 0.2 s) t1 = 1 = 416.7 s 2,400 t2 = 12.8 2 = 25.6 s t1 + t2 = 2,212 (clocks) t cy t1 t2 parity stop d7 d6 d2 d1 d0 r x d (input) intsr intser (when framing/ overrun error occurs) intser (when parity error occurs) start 467 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud [example] ei main processing intser generated uart receive error interrupt (intser) servicing seven cpu clocks (min.) (time from generation of interrupt request to processing) reti mov a, rxb instructions of 2,205 cpu clocks (min.) are necessary. 468 chapter 19 serial interface channel 2 user's manual u12013ej3v2ud 19.4.5 restrictions in uart mode 2 to use the txd1/stb/p23 pin to output uart data by using the time-division transfer function, perform the following processing when the transmit operation is enabled and when the transmit/receive operation is stopped. the output circuit of the alternate function of this txd1/stb/p23 pin differs between the actual device and the in- circuit emulator (see figure 19-17). therefore, delete the underlined part in the examples below when executing emulation with the in-circuit emulator (ie). condition: serial interface pin select register (sips) = 20h or 30h (when using txd1 pin as output pin for uart transmission) (1) when transmit operation is enabled clr1 pm2.3 ; sets p23 (txd1) pin to output mode. set1 p2.3 ; sets output latch of p23 to 1 . set1 asim.7 ; enables transmission (txe = 1). clr1 p2.3 ; this line is necessary only for the actual device. delete it when the ie is used. mov txs, #byte ; transfers transmit data (#byte) to transmit shift register. cautions 1. perform this processing each time a transmit operation is enabled by using the txd1 pin as an output pin. 2. perform this processing each time the output pin is switched from the txd0 pin to the txd1 pin because the transmit operation must be stopped once and then enabled again. (2) when transmit operation is stopped set1 p2.3 ; this line is necessary only for the actual device. delete it when the ie is used. clr1 asim.7 ; stops transmission (txe = 0). cautions 1. perform this processing each time a transmit operation is enabled by using the txd1 pin as an output pin. 2. perform this processing each time the output pin is switched from the txd0 pin to the txd1 pin because the transmit operation must be stopped once and then enabled again. figure 19-17. p23 output selector p23/stb/txd1 pm23 alternate output signal (txd1) output latch of p23 p23/stb/txd1 pm23 alternate output signal (txd1) output latch of p23 (actual device) (in-circuit emulator) 469 user's manual u12013ej3v2ud chapter 20 real-time output port 20.1 real-time output port functions data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with the generation of a timer interrupt request or external interrupt request, then output externally. this is called the real-time output function. the pins that output data externally are called real-time output ports. by using a real-time output, a signal which has no jitter can be output. this port is therefore suitable for control of stepper motors, etc. port mode/real-time output port mode can be specified in 1-bit units. 470 chapter 20 real-time output port user's manual u12013ej3v2ud 20.2 real-time output port configuration the real-time output port consists of the following hardware. table 20-1. real-time output port configuration item configuration register real-time output buffer register (rtbl, rtbh) control registers port mode register 12 (pm12) real-time output port mode register (rtpm) real-time output port control register (rtpc) figure 20-1. real-time output port block diagram internal bus real-time output port control register extr byte output trigger controller real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) output latch p120 p127 real-time output port mode register (rtpm) intp2 inttm1 inttm2 port mode register 12 (pm12) 471 chapter 20 real-time output port user's manual u12013ej3v2ud (1) real-time output buffer registers (rtbl, rtbh) the addresses of rtbl and rtbh are mapped individually in the special function register (sfr) area as shown in figure 20-2. when specifying 4 bits 2 channels as the operating mode, data is set individually to rtbl and rtbh. when specifying 8 bits 1 channel as the operating mode, data is set to both rtbl and rtbh by writing 8- bit data to either rtbl or rtbh. table 20-2 shows the operations during manipulation of rtbl and rtbh. figure 20-2. real-time output buffer register configuration table 20-2. operation in real-time output buffer register manipulation operating mode register to be reading note 1 writing note 2 manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits 4 bits 2 channels rtbl rtbh rtbl invalid rtbl rtbh rtbh rtbl rtbh invalid 8 bits 1 channel rtbl rtbh rtbl rtbh rtbl rtbh rtbh rtbl rtbh rtbl notes 1. only the bits set in the real-time output port mode can be read. when a bit set in the port mode is read, 0 is read. 2. after setting data in the real-time output port, output data should be set to rtbl and rtbh by the time a real-time output trigger is generated. higher 4 bits lower 4 bits rtbl rtbh ff30h ff31h 472 chapter 20 real-time output port user's manual u12013ej3v2ud 20.3 real-time output port control registers the following three registers control the real-time output port. ? port mode register 12 (pm12) ? real-time output port mode register (rtpm) ? real-time output port control register (rtpc) (1) port mode register 12 (pm12) this register sets the input or output mode of the port 12 pins (p120 to p127) which function alternately as real-time output pins (rtp0 to rtp7). to use port 12 as a real-time output port, the port pin that performs real-time output must be set in the output mode (pm12n = 0: n = 0 to 7). pm12 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm12 to ffh. figure 20-3. format of port mode register 12 (2) real-time output port mode register (rtpm) this register selects the real-time output port mode/port mode in 1-bit units. rtpm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears rtpm to 00h. figure 20-4. format of real-time output port mode register cautions 1. when using these bits as a real-time output port, set the ports at which real-time output is performed to the output mode (clear the corresponding bit of port mode register 12 (pm12) to 0). 2. in ports specified as real-time output ports, data cannot be set to the output latch. therefore, when setting an initial value, data should be set to the output latch before setting the real-time output mode. 7 rtpm7 6 rtpm6 5 rtpm5 4 rtpm4 3 rtpm3 2 rtpm2 1 rtpm1 0 rtpm0 symbol rtpm address ff34h 00h after reset r/w r/w rtpmn 0 1 port mode real-time output port mode real-time output port selection (n = 0 to 7) 7 pm127 6 pm126 5 pm125 4 pm124 3 pm123 2 pm122 1 pm121 0 pm120 symbol pm12 address ff2ch after reset ffh r/w r/w pm12n 0 1 output mode (output buffer on) input mode (output buffer off) selection of i/o mode of p12n pin (n = 0 to 7) 473 chapter 20 real-time output port user's manual u12013ej3v2ud (3) real-time output port control register (rtpc) this register sets the real-time output port operating mode and output trigger. table 20-3 shows the relationship between the operating mode of the real-time output port and output trigger. rtpc is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears rtpc to 00h. figure 20-5. format of real-time output port control register table 20-3. real-time output port operating mode and output trigger byte extr operating mode rtbh port output rtbl port output 0 0 4 bits 2 channels inttm2 inttm1 1 inttm1 intp2 1 0 8 bits 1 channel inttm1 1 intp2 7 0 symbol rtpc 6 0 5 0 4 0 3 0 2 0 <1> byte <0> extr address ff36h 00h after reset r/w r/w extr 0 1 real-time output control by intp2 intp2 not specified as real-time output trigger intp2 specified as real-time output trigger byte 0 1 real-time output port operating mode 4 bits 2 channels 8 bits 1 channel 474 user's manual u12013ej3v2ud chapter 21 interrupt and test functions 21.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in the interrupt disabled status. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt source from the watchdog timer is provided as a non-maskable interrupt source. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). high-priority interrupts can be given priority over to low priority interrupts by using multiple interrupt servicing. if two or more interrupts with the same priority are generated simultaneously, each interrupt has a predeter- mined priority (see table 21-1 ). a standby release signal is generated. six external interrupt sources and thirteen internal interrupt sources are provided as maskable interrupt sources. (3) software interrupt this is a vectored interrupt that occurs when the brk instruction is executed. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control. 475 chapter 21 interrupt and test functions user's manual u12013ej3v2ud table 21-1. interrupt source list (1/2) interrupt default interrupt source internal/ type priority note 1 name trigger external non- intwdt watchdog timer overflow (with internal 0004h (a) maskable watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (with (b) interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intcsi0 end of serial interface channel 0 internal 0014h (b) transfer 8 intcsi1 end of serial interface channel 1 0016h transfer 9 intser occurrence of serial interface channel 2 0018h uart reception error 10 intsr end of serial interface channel 2 001ah uart reception intcsi2 end of serial interface channel 2 3-wire transfer 11 intst end of serial interface channel 2 001ch uart transfer 21.2 interrupt sources and configuration a total of 21 non-maskable, maskable, and software interrupts are provided as interrupt sources (see table 21-1 ). vector table address basic configuration type note 2 notes 1. the default priority is the priority used when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 21-1. 476 chapter 21 interrupt and test functions user's manual u12013ej3v2ud table 21-1. interrupt source list (2/2) interrupt default interrupt source internal/ type priority note 1 name trigger external maskable 12 inttm3 reference time interval signal from internal 001eh (b) watch timer 13 inttm00 generation of 16-bit timer register, 0020h capture/compare register 00 (cr00) match signal 14 inttm01 generation of 16-bit timer register, 0022h capture/compare register 01 (cr01) match signal 15 inttm1 generation of 8-bit timer/event 0024h counter 1 match signal 16 inttm2 generation of 8 bit timer/event 0026h counter 2 match signal 17 intad end of a/d converter conversion 0028h software brk brk instruction execution 003eh (e) vector table address basic configuration type note 2 notes 1. the default priority is the priority used when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 21-1. 477 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority controller vector table address generator standby release si g nal interrupt request internal bus ie pr isp mk if interrupt request priority controller vector table address generator standby release si g nal internal bus ie pr isp mk if priority controller vector table address generator standby release si g nal interrupt request sampling clock edge detector sampling clock select register (scs) external interrupt mode register (intm0) 478 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt remark if: interrupt request flag ie: interrupt enable flag isp: inservice priority flag mk: interrupt mask flag pr: priority specification flag external interrupt mode register (intm0, intm1) edge detector interrupt request ie pr isp mk if priority controller vector table address generator standby release signal internal bus internal bus priority controller vector table address generator interrupt request 479 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. interrupt request flag register (if0l, if0h, if1l) interrupt mask flag register (mk0l, mk0h, mk1l) priority specification flag register (pr0l, pr0h, pr1l) external interrupt mode register (intm0, intm1) sampling clock select register (scs) program status word (psw) table 21-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 21-2. various flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt tmif4 if0l tmmk4 mk0l tmpr4 pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intcsi0 csiif0 if0h csimk0 mk0h csipr0 pr0h intcsi1 csiif1 csimk1 csipr1 intser serif sermk serpr intsr/intcsi2 srif srmk srpr intst stif stmk stpr inttm3 tmif3 tmmk3 tmpr3 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm1 tmif1 if1l tmmk1 mk1l tmpr1 pr1l inttm2 tmif2 tmmk2 tmpr2 intad adif admk adpr 480 chapter 21 interrupt and test functions user's manual u12013ej3v2ud note wtif is the test input flag. a vectored interrupt request is not generated. cautions 1. the tmif4 flag is r/w enabled only when the watchdog timer is used as an interval timer. if the watchdog timer is used in watchdog timer mode 1, clear the tmif4 flag to 0. 2. be sure to clear if0l bit 7 and if1l bits 3 to 6 to 0. 3. when an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then servicing of the interrupt routine is started. (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set with a 1-bit or an 8-bit memory manipulation instruction. if if0l and if0h are used as the 16-bit register if0, use a 16-bit memory manipulation instruction for setting. reset input clears these registers to 00h. figure 21-2. format of interrupt request flag register 7 0 symbol if0l <6> pif5 <5> pif4 <4> pif3 <3> pif2 <2> pif1 <1> pif0 <0> tmif4 address ffe0h 00h after reset r/w r/w if 0 1 interrupt request flag no interrupt request signal interrupt request signal is generated; interrupt request state <7> tmif01 if0h <6> tmif00 <5> tmif3 <4> stif <3> srif <2> serif <1> csiif1 <0> csiif0 <7> wtif note if1l 6 0 5 0 4 0 3 0 <2> adif <1> tmif2 <0> tmif1 ffe1h 00h r/w ffe2h 00h r/w 481 chapter 21 interrupt and test functions user's manual u12013ej3v2ud note wtmk controls standby mode release enable/disable; it does not control the interrupt function. cautions 1. if the tmmk4 flag is read when the watchdog timer is used in watchdog timer mode 1, the mk0 value becomes undefined. 2. because port 0 also functions as an external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. be sure to set mk0l bit 7 and mk1l bits 3 to 6 to 1. (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l, mk0h, and mk1l are set with a 1-bit or an 8-bit memory manipulation instruction. if mk0l and mk0h are used as the 16-bit register mk0, use a 16-bit memory manipulation instruction for setting. reset input sets these registers to ffh. figure 21-3. format of interrupt mask flag register 7 1 symbol mk0l <6> pmk5 <5> pmk4 <4> pmk3 <3> pmk2 <2> pmk <1> pmk <0> tmmk4 address ffe4h ffh after reset r/w r/w mk 0 1 interrupt servicing control interrupt servicing enabled interrupt servicing disabled <7> tmmk01 mk0h <6> tmmk00 <5> tmmk3 <4> stmk <3> srmk <2> sermk <1> csimk1 <0> csimk0 <7> wtmk note mk1l 6 1 5 1 4 1 3 1 <2> admk <1> tmmk2 <0> tmmk1 ffe5h ffh r/w ffe6h ffh r/w 482 chapter 21 interrupt and test functions user's manual u12013ej3v2ud cautions 1. if the watchdog timer is used in watchdog timer mode 1, set the tmpr4 flag to 1. 2. be sure to set pr0l bit 7 and pr1l bits 3 to 7 to 1. (3) priority specification flag registers (pr0l, pr0h, and pr1l) the priority specification flags are used to set the corresponding maskable interrupt priorities. pr0l, pr0h, and pr1l are set with a 1-bit or an 8-bit memory manipulation instruction. if pr0l and pr0h are used as the 16-bit register pr0, use a 16-bit memory manipulation instruction for setting. reset input sets these registers to ffh. figure 21-4. format of priority specification flag register 7 1 symbol pr0l <6> ppr5 <5> ppr4 <4> ppr3 <3> ppr2 <2> ppr1 <1> ppr0 <0> tmpr4 address ffe8h ffh after reset r/w r/w 0 1 priority level selection high priority level low priority level <7> tmpr01 pr0h <6> tmpr00 <5> tmpr3 <4> stpr <3> srpr <2> serpr <1> csipr1 <0> csipr0 7 1 pr1l 6 1 5 1 4 1 3 1 <2> adpr <1> tmpr2 <0> tmpr1 ffe9h ffh r/w ffeah ffh r/w pr 483 chapter 21 interrupt and test functions user's manual u12013ej3v2ud (4) external interrupt mode registers (intm0, intm1) these registers set the valid edge for intp0 to intp5, ti00, and ti01. intm0 specifies the valid edges of interrupt pins intp0 to intp2, ti00, and ti01, and intm1 specifies the valid edges of intp3 to intp5. intm0 and intm1 are set with an 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 21-5. format of external interrupt mode register 0 caution when using the ti00/p00/intp0 and ti01/p01/intp1 pins as timer input pins (ti00 and ti01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (tmc01 to tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0, 0, before setting the valid edge of ti00 and ti01. the valid edge is set by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). when using the ti00/p00/intp0 and ti01/p01/intp1 pins as external interrupt input pins (intp0 and intp1), the valid edge of intp0 and intp1 may be set while 16-bit timer 0 is operating. address ffech 00h after reset r/w r/w 0 0 1 1 intp0/ti00 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es11 7 es31 symbol intm0 6 es30 5 es21 4 es20 3 es11 2 es10 1 0 0 0 0 1 0 1 es10 0 0 1 1 intp1/ti01 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es21 0 1 0 1 es20 0 0 1 1 intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es31 0 1 0 1 es30 484 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-6. format of external interrupt mode register 1 address ffedh 00h after reset r/w r/w 0 0 1 1 intp3 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es41 7 0 symbol intm1 6 0 5 es61 4 es60 3 es51 2 es50 1 es41 0 es40 0 1 0 1 es40 0 0 1 1 intp4 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es51 0 1 0 1 es50 0 0 1 1 intp5 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es61 0 1 0 1 es60 485 chapter 21 interrupt and test functions user's manual u12013ej3v2ud caution f xx /2 n is the clock supplied to the cpu and f xx /2 5 , f xx /2 6 , and f xx /2 7 are clocks supplied to the peripheral hardware. f xx /2 n stops in the halt mode. remarks 1. n: value (n = 0 to 4) of bits 0 to 2 (pcc0 to pcc2) of processor clock control register (pcc) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs: bit 0 of the oscillation mode select register (osms) 5. values in parentheses apply to operation with f x = 5.0 mhz. (5) sampling clock select register (scs) this register is used to set the clock for sampling the valid edge input to intp0. when remote controlled data reception is carried out using intp0, digital noise is eliminated using the sampling clock. scs is set with an 8-bit memory manipulation instruction. reset input clears scs to 00h. figure 21-7. format of sampling clock select register address ff47h 00h after reset r/w r/w 0 0 1 1 intp0 sampling clock selection f xx /2 n f xx /2 7 f xx /2 5 f xx /2 6 scs1 7 0 symbol scs 6 0 5 0 4 0 3 0 2 0 1 scs1 0 scs0 0 1 0 1 scs0 mcs = 1 mcs = 0 f x /2 7 (39.1 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 8 (19.5 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 486 chapter 21 interrupt and test functions user's manual u12013ej3v2ud (b) when input is equal to or twice the sampling cycle (t smp ) when the sampled intp0 input level is the active level twice in succession, the noise eliminator sets the interrupt request flag (pif0) to 1. figure 21-8 shows the i/o timing of the noise eliminator. figure 21-8. noise eliminator i/o timing (during rising edge detection) (a) when input is less than the sampling cycle (t smp ) (c) when input is more than twice the cycle frequency (t smp ) t smp sampling clock intp0 pif0 l because the intp0 level is not high when it is sampled, pif0 output remains at low level. t smp sampling clock intp0 pif0 because the intp0 level is high twice in succession, the pif0 fla g is set to 1. t smp sampling clock intp0 pif0 because the sampled intp0 level is high twice in succession in <2>, the pif0 fla g is set to 1. <1> <2> 487 chapter 21 interrupt and test functions user's manual u12013ej3v2ud (6) program status word (psw) the program status word is a register used to hold the instruction execution result and the current status of an interrupt request. the ie flag, which sets maskable interrupt enable/disable, and the isp flag, which controls multiple interrupt servicing, are mapped to the psw. besides 8-bit unit read/write, this register can also be manipulated by a bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged or when the brk instruction is executed, the contents of the psw are automatically saved to the stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the contents of the psw can also be saved into the stack with the push psw instruction. the contents are reset from the stack with the reti, retb, and pop psw instructions. reset input sets the psw to 02h. figure 21-9. format of program status word 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy 02h after reset isp 0 used when normal instruction is executed priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupts disabled) 1 interrupt request not acknowledged or low-priority interrupt servicing (all maskable interrupts enabled) ie interrupt request acknowledge enable/disable 0 disabled 1 enabled 488 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.4 interrupt servicing operations 21.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally acknowledged even if interrupt requests are in an acknowl- edgment disabled state. it does not undergo interrupt priority control and has the highest priority of all interrupts. if a non-maskable interrupt request is acknowledged, the contents of the acknowledged interrupt are saved in the stack, psw and pc, in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into the pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. figure 21-10 shows the flowchart illustrating how a non-maskable interrupt request occurs and is acknowledged. figure 21-11 shows the acknowledgment timing of a non-maskable interrupt request. figure 21-12 shows the acknowledgment operation of multiple non-maskable interrupt requests. 489 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-10. non-maskable interrupt request occurrence and acknowledgment flowchart wdtm: watchdog timer mode register wdt: watchdog timer figure 21-11. non-maskable interrupt request acknowledgment timing wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdtm3 = 0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt servicing start interrupt request held pending reset processing interval timer start no yes yes no yes no yes no yes no instruction instruction cpu instruction tmif4 psw and pc save, jump to interrupt servicing interrupt servicing program an interrupt request generated during this period is acknowledged at the timing marked . tmif4 : watchdog timer interrupt request flag 490 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-12. non-maskable interrupt request acknowledgment operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> 1 instruction execution nmi request <2> nmi request <1> execution nmi request <2> held pending pending nmi request <2> serviced main routine nmi request <1> 1 instruction execution nmi request <2> nmi request <1> execution nmi request <2> held pending nmi request <3> held pending pending nmi request <2> serviced nmi request <3> nmi request <3> is not acknowledged (nmi request is acknowledged only once even if it occurs twice or more). 491 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request becomes acknowledgeable when the corresponding interrupt request flag is set to 1 and the corresponding interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enabled state (with the ie flag set to 1). however, a low-priority interrupt is not acknowledged during high-priority interrupt servicing (with the isp flag reset to 0). wait times from maskable interrupt request generation to interrupt servicing are shown in table 21-3. for the timing to acknowledge an interrupt request, see figures 21-14 and 21-15 . table 21-3. times from maskable interrupt request generation to interrupt servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes the maximum. remark 1 clock: (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified as higher priority with the priority specification flag is acknowledged first. if two or more requests specified as the same priority by the interrupt priority specification flag are generated simultaneously, the one with the higher default priority is acknowl- edged first. any pending interrupt requests are acknowledged when they become acknowledgeable. figure 21-13 shows an interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the contents of acknowledged interrupt are saved in the stack, program status word (psw) and program counter (pc), in that order, the ie flag is reset to 0, and the acknowledged interrupt priority specification flag contents are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into the pc and branched. restoration from the interrupt is possible with the reti instruction. 1 f cpu 492 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-13. interrupt request acknowledgment processing algorithm if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls maskable interrupt request acknowledge (1 = enable, 0 = disable) isp: flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority is being serviced. 1 = interrupt request is not acknowledged or interrupt with low priority being serviced). start if = 1? mk = 0? pr = 0? any simultaneously generated pr = 0 interrupt requests? any simultaneously generated high-priority interrupt requests? ie = 1? isp = 1? vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high- priority interrupt among simultaneously generated pr = 0 interrupt requests? ie = 1? yes (high priority) yes no yes no no no yes (interrupt request generation) no yes no (low priority) yes yes no yes yes no no 493 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-14. interrupt request acknowledgment timing (minimum time) remark 1 clock: (f cpu : cpu clock) figure 21-15. interrupt request acknowledgment timing (maximum time) remark 1 clock: (f cpu : cpu clock) f cpu 1 f cpu 1 instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing if ( pr = 1) if ( pr = 0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing if ( pr = 1) if ( pr = 0) 25 clocks 494 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.4.3 software interrupt request acknowledgment operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents of the acknowledged interrupt are saved in the stack, program status word (psw) and program counter (pc), in that order, the ie flag is reset to 0 and the contents of the vector tables (003eh and 003fh) are loaded into the pc and branched. restoration from the software interrupt is possible with the retb instruction. caution do not use the reti instruction for restoring from the software interrupt. 21.4.4 multiple interrupt servicing acknowledging another interrupt request while one interrupt is being serviced is called multiple interrupt servicing. multiple interrupt servicing does not occur unless interrupt requests are enabled (ie = 1) (except the non-maskable interrupt). when an interrupt request is acknowledged, the other interrupts are disabled (ie = 0). to enable multiple interrupt servicing, therefore, the ie flag must be set to 1 by executing the ei instruction during interrupt servicing and interrupts must be enabled. even if interrupt requests are enabled, multiple interrupt servicing may not be possible. however, this is controlled by the programmable priority. an interrupt has two types of priorities: the default priority and the programmable priority. multiple interrupt servicing is controlled by the programmable priority. in the ei status, if an interrupt request with a priority that is the same or higher than that of the interrupt currently being serviced is generated, the interrupt is acknowledged for multiple interrupt servicing. if an interrupt request with a priority lower than that of the interrupt currently being serviced is generated, the interrupt is not acknowledged for multiple interrupt servicing. if interrupts are disabled, or if multiple interrupt servicing is not enabled because the interrupt has a low priority, the interrupt is held pending. after the servicing of the current interrupt has been completed, and after one instruction of the main processing has been executed, the pending interrupt is acknowledged. multiple interrupt servicing is not enabled while a non-maskable interrupt is being serviced. table 21-4 shows the interrupt requests enabled for multiple interrupt servicing. figure 21-16 shows multiple interrupt servicing examples. table 21-4. interrupt request enabled for multiple interrupt servicing during interrupt servicing non-maskable maskable interrupt request interrupt pr = 0 pr = 1 request ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d maskable interrupt isp = 0 e e d d d isp = 1 e e d e d software interrupt e e d e d remarks 1. e: multiple interrupt servicing enabled 2. d: multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw isp = 0: an interrupt with a higher priority is being serviced isp = 1: an interrupt request is not acknowledged or an interrupt with a lower priority is being serviced ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled 4. pr is a flag contained in pr0l, pr0h, and pr1l pr = 0: higher priority level pr = 1: lower priority level interrupt being serviced multiple interrupt request 495 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-16. multiple interrupt servicing example (1/2) example 1. multiple interrupt servicing occurs twice two interrupt requests, intyy and intzz, are acknowledged while the intxx interrupt is being serviced. before each interrupt request is acknowledged, the ei instruction is always issued and interrupt requests are enabled. example 2. multiple interrupt servicing does not occur because of interrupt priority intyy, which occurs while intxx is being serviced is not acknowledged for multiple interrupt servicing because the priority of intyy is lower than that of intxx. intyy is held pending and is acknowledged after one instruction of the main processing has been executed. pr = 0: high-priority interrupt pr = 1: low-priority interrupt ie = 0: interrupt acknowledgment disabled main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti 496 chapter 21 interrupt and test functions user's manual u12013ej3v2ud figure 21-16. multiple interrupt servicing example (2/2) example 3. multiple interrupt servicing does not occur because interrupts are not enabled in the servicing of intxx, other interrupts are not enabled (the ei instruction is not executed). therefore, intyy is not acknowledged for multiple interrupt servicing. this interrupt is held pending and acknowledged after one instruction of the main processing has been executed. pr = 0: high-priority interrupt ie = 0: interrupt acknowledgment disabled main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei 497 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.4.5 interrupt request pending for some instructions, even if an interrupt is generated while that instruction is being executed, the interrupt is held pending until execution of the next instruction is completed. the instructions that hold interrupt requests pending (interrupt request pending) are shown below. mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1 cy, psw.bit and1 cy, psw.bit or1 cy, psw.bit xor1 cy, psw.bit set1 psw.bit clr1 psw.bit retb reti push psw pop psw bt psw.bit, $addr16 bf psw.bit, $addr16 btclr psw.bit, $addr16 ei di manipulation instructions for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, intm0, intm1 registers caution the brk instruction is not an interrupt request pending instruction. however, the ie flag is cleared to 0 by a software interrupt that is started by brk instruction execution. thus, even if a maskable interrupt request is generated during brk instruction execution, that interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. figure 21-17 shows the timing at which an interrupt request is held pending. figure 21-17. interrupt request pending timing remarks 1. instruction n: instruction that holds interrupts requests pending 2. instruction m: instructions other than instruction n 3. the pr (priority level) values do not affect the operation of if (interrupt request). cpu processing if instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program 498 chapter 21 interrupt and test functions user's manual u12013ej3v2ud 21.5 test function when the watch timer overflows and the port 4 falling edge is detected, the internal test input flag is set to 1, and the standby release signal is generated. unlike the interrupt function, vectored processing is not performed. there are two test input sources as shown in table 21-5. the basic configuration is shown in figure 21-18. table 21-5. test input sources test input sources internal/ name trigger external intwt watch timer overflow internal intpt4 falling edge detection at port 4 external figure 21-18. basic configuration of test function remark if: test input flag mk: test mask flag 21.5.1 registers controlling test function the test function is controlled by the following three registers. interrupt request flag register 1l (if1l) interrupt mask flag register 1l (mk1l) key return mode register (krm) the names of the test input flags and test mask flags corresponding to the test input signals are listed in table 21-6. table 21-6. flags corresponding to test input signals test input signal name test input flag test mask flag intwt wtif wtmk intpt4 krif krmk internal bus mk if test input signal standby release signal 499 chapter 21 interrupt and test functions user's manual u12013ej3v2ud (1) interrupt request flag register 1l (if1l) this register indicates whether a watch timer overflow is detected or not. if1l is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears if1l to 00h. figure 21-19. format of interrupt request flag register 1l caution be sure to clear bits 3 to 6 to 0. (2) interrupt mask flag register 1l (mk1l) this register is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer. mk1l is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mk1l to ffh. figure 21-20. format of interrupt mask flag register 1l caution be sure to set bits 3 to 6 to 1. <7> wtif symbol if1l 6 0 5 0 4 0 3 0 <2> adif <1> tmif2 <0> tmif1 address ffe2h 00h after reset r/w r/w 0 1 watch timer overflow detection flag not detected detected wtif <7> wtmk symbol mk1l 6 1 5 1 4 0 3 0 <2> admk <1> tmmk2 <0> tmmk1 address ffe6h ffh after reset r/w r/w 0 1 standby mode control by watch timer releasing the standby mode enabled releasing the standby mode disabled wtmk 500 chapter 21 interrupt and test functions user's manual u12013ej3v2ud (3) key return mode register (krm) this register is used to set enable/disable of standby function clear by the key return signal (port 4 falling edge detection). krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 21-21. format of key return mode register caution when port 4 falling edge detection is used, be sure to clear krif to 0 (it is not cleared to 0 automatically). 21.5.2 test input signal acknowledgment operation (1) internal test signal (intwt) intwt is generated when the watch timer overflows, and sets the wtif flag. unless interrupts are masked by the interrupt mask flag (wtmk) at this time, the standby release signal is generated. the watch function is realized by checking the wtif flag at a shorter cycle than the watch timer overflow cycle. (2) external test input signal (intpt4) intpt4 is generated when a falling edge is input to the port 4 pins (p40 to p47), and krif is set. unless interrupts are masked by the interrupt mask flag (krmk) at this time, the standby release signal is generated. if port 4 is used as a key matrix return signal input, whether or not a key input has been applied can be checked from the krif status. 7 0 symbol krm 6 0 5 0 4 0 3 0 2 0 <1> krmk <0> krif address fff6h 02h after reset r/w r/w 0 1 key return signal not detected detected (port 4 falling edge detection) krif 0 1 standby mode control by key return signal standby mode release enabled standby mode release disabled krmk 501 user's manual u12013ej3v2ud chapter 22 external device expansion function 22.1 external device expansion function the external device expansion function connects external devices to areas other than the internal rom, ram, and sfr. ports 4 to 6 are used for connection of external devices. ports 4 to 6 control addresses/data, the read/ write strobe, wait, address strobe etc. table 22-1. pin functions in external memory expansion mode pin function when external device is connected alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 22-2. state of port 4 to 6 pins in external memory expansion mode ports and bits port 4 port 5 port 6 0 to 7 0 1 2 3 4 5 6 7 0 to 3 4 to 7 single-chip mode port port port port 256-byte expansion mode address/data port port rd, wr, wait, astb 4 kb expansion mode address/data address port port rd, wr, wait, astb 16 kb expansion mode address/data address port port rd, wr, wait, astb full-address mode address/data address port rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port in all modes. external expansion modes 502 chapter 22 external device expansion function user's manual u12013ej3v2ud memory maps when using the external device expansion function are as follows. figure 22-1. memory map when using external device expansion function (1/3) (a) memory map of pd780053 and 780053y, (b) memory map of pd780054 and 780054y, and pd780058, 780058b, 780058by, and pd780058, 780058b, 780058by, 78f0058, and 78f0058y with internal rom 78f0058, and 78f0058y with internal rom (flash memory) set to 24 kb (flash memory) set to 32 kb ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh a000h 9fffh 0000h reserved internal buffer ram reserved full-address mode (when mm2 to mm0 = 111) single-chip mode 16 kb expansion mode (when mm2 to mm0 = 101) 7000h 6fffh 6100h 60ffh 6000h 5fffh 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh c000h bfffh 0000h reserved internal buffer ram reserved full-address mode (when mm2 to mm0 = 111) single-chip mode 16 kb expansion mode (when mm2 to mm0 = 101) 9000h 8fffh 8100h 80ffh 8000h 7fffh 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) 503 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-1. memory map when using external device expansion function (2/3) (c) memory map of pd780055 and 780055y, (d) memory map of pd780056 and 780056y, and pd780058, 780058b, 780058by, and pd780058, 780058b, 780058by, 78f0058, and 78f0058y with internal rom 78f0058, and 78f0058y with internal rom (flash memory) set to 40 kb (flash memory) set to 48 kb ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh e000h dfffh 0000h reserved internal buffer ram reserved full-address mode (when mm2 to mm0 = 111) single-chip mode 16 kb expansion mode (when mm2 to mm0 = 101) b000h afffh a100h a0ffh a000h 9fffh 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh d000h cfffh c100h c0ffh c000h bfffh 0000h reserved internal buffer ram reserved full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) single-chip mode 256-byte expansion mode (when mm2 to mm0 = 011) 504 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-1. memory map when using external device expansion function (3/3) (e) pd780058, 780058b, 780058by, 78f0058, (f) pd780058, 780058b, 780058by, 78f0058, 78f0058y memory map when internal rom 78f0058y memory map when internal rom (flash memory) size is 56 kb (flash memory) size is 60 kb caution when the internal rom (flash memory) size is 60 kb, the area from f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom (flash memory) size to 56 kb or less using the internal memory size switching register (ims). sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh f000h efffh e100h f0ffh e000h dfffh 0000h reserved internal buffer ram reserved internal expansion ram full-address mode (when mm2 to mm0 = 111) or 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh f000h efffh 0000h reserved internal buffer ram reserved internal expansion ram single-chip mode reserved ffffh 505 chapter 22 external device expansion function user's manual u12013ej3v2ud 22.2 external device expansion function control register the external device expansion function is controlled by the memory expansion mode register (mm) and internal memory size switching register (ims). (1) memory expansion mode register (mm) mm sets the wait count and external expansion area, and also sets the input/output mode of port 4. mm is set with a 1-bit memory or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 22-2. format of memory expansion mode register note the full-address mode allows external expansion to the entire 64 kb address space except for the internal rom, ram, and sfr areas and the reserved areas. remark p60 to p63 are used as port pins without regard to the mode (single-chip mode or memory expansion mode). 7 0 symbol mm 6 0 5 pw1 4 pw0 3 0 2 mm2 1 mm1 0 mm0 address fff8h 10h after reset r/w r/w mm2 mm1 mm0 single-chip/ memory expansion mode selection p40 to p47, p50 to p57, p64 to p67 pin state p40 to p47 p50 to p53 p54, p55 p56, p57 p64 to p67 000 001 011 100 101 111 single-chip mode 256-byte mode 4 kb mode 16 kb mode full- address mode note memory expansion mode port mode input output port mode port mode port mode port mode ad0 to ad7 a8 to a11 a12, a13 a14, a15 p64 = rd p65 = wr p66 = wait p67 = astb other than above setting prohibited pw1 pw0 00 01 10 11 wait control no wait wait (one wait state insertion) setting prohibited wait control by external wait pin 506 chapter 22 external device expansion function user's manual u12013ej3v2ud (2) internal memory size switching register (ims) this register specifies the internal memory size. in principle, use ims in the default status. however, when using the external device expansion function with the pd780058, 780058b, and 780058by, set ims so that the internal rom capacity is 56 kb or less. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to the value indicated in table 22-3. figure 22-3. format of internal memory size switching register note the values after reset depend on the product (see table 22-3 ). table 22-3. values after internal memory size switching register is reset part number reset value pd780053, 780053y c6h pd780054, 780054y c8h pd780055, 780055y cah pd780056, 780056y cch pd780058, 780058b, 780058by cfh 1 1 48 kb 56 kb 1 1 0 1 0 0 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h note after reset r/w r/w internal rom size selection rom3 60 kb 1 rom2 1 rom1 1 rom0 1 setting prohibited other than above internal high-speed ram size selection ram2 ram1 ram0 1,024 bytes 110 setting prohibited other than above 1 1 32 kb 40 kb 0 0 0 1 0 0 0 24 kb 110 507 chapter 22 external device expansion function user's manual u12013ej3v2ud 22.3 external device expansion function timing the timing control signal output pins in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output upon the occurrence of data accesses and instruction fetches from external memory. during internal memory access, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output upon the occurrence of data access to external memory. during internal memory access, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an i/o port. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. the astb signal is output without regard to data accesses and instruction fetches from external memory. the astb signal is also output when the internal memory is accessed. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pin. a valid signal is output or input during data accesses and instruction fetches from external memory. these signals change when the internal memory is accessed (output values are undefined). the timing charts are shown in figures 22-4 to 22-7. 508 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-4. instruction fetch from external memory (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb rd ad0 to ad7 a8 to a15 lower address operation code higher address astb rd ad0 to ad7 a8 to a15 lower address operation code higher address internal wait signal ( 1-clock wait ) astb rd lower address operation code ad0 to ad7 a8 to a15 higher address wait 509 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-5. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting higher address astb rd ad0 to ad7 a8 to a15 lower address read data astb rd ad0 to ad7 a8 to a15 lower address read data higher address internal wait signal (1-clock wait) astb rd lower address read data ad0 to ad7 a8 to a15 higher address wait 510 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-6. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb wr ad0 to ad7 a8 to a15 lower address write data hi-z higher address astb wr ad0 to ad7 a8 to a15 lower address write data higher address internal wait signal ( 1-clock wait ) hi-z astb wr higher address ad0 to ad7 a8 to a15 wait hi-z lower address write data 511 chapter 22 external device expansion function user's manual u12013ej3v2ud figure 22-7. external memory read modify write timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb rd wr ad0 to ad7 a8 to a15 lower address write data higher address hi-z read data lower address higher address internal wait signal ( 1-clock wait ) hi-z astb rd wr ad0 to ad7 a8 to a15 write data read data astb rd wr higher address ad0 to ad7 a8 to a15 wait hi-z lower address write data read data 512 chapter 22 external device expansion function user's manual u12013ej3v2ud 22.4 example of connection with memory figure 22-8 shows an example of the connection between the pd780054 and external memory. sram is used as the external memory in this diagram. in addition, the external device expansion function is used in the full-address mode, and the addresses from 0000h to 7fffh (32 kb) are allocated to internal rom, and the addresses after 8000h to sram. figure 22-8. example of connection between pd780054 and memory pd43256b cs oe a0 to a14 i/o1 to i/o8 we address bus v dd pd780054 74hc573 le d0 to d7 q0 to q7 oe rd wr a8 to a14 astb ad0 to ad7 data bus 513 user's manual u12013ej3v2ud chapter 23 standby function 23.1 standby function and configuration 23.1.1 standby function the standby function is designed to decrease the power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is used to stop the cpu operation clock. the system clock oscillator continues oscillating. in this mode, the current consumption cannot be decreased as much as in the stop mode, but the halt mode is effective for restarting immediately upon interrupt request and to carry out intermittent operations such as in watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops and the whole system stops. the cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 1.8 v) is possible. thus, the stop mode is effective for holding data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure oscillation stabilization after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the registers, flags and data memory just before standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates on the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when shifting to the stop mode, be sure to stop the peripheral hardware operation before executing the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (cs) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 514 chapter 23 standby function user's manual u12013ej3v2ud 23.1.2 standby function control register the wait time after the stop mode is released upon interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /f x , not 2 18 /f x , until the stop mode is released by reset input. figure 23-1. format of oscillation stabilizat time select register caution the wait time that elapses when the stop mode is released does not include the time required for the clock to start oscillation (see ??in the illustration below) after the stop mode is released. the same applies when the stop mode is released by reset input and by generation of an interrupt request. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs: bit 0 of the oscillation mode select register (osms) 4. values in parentheses apply to operation with f x = 5.0 mhz address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time when stop mode is released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 mcs = 1 mcs = 0 2 12 /f x (819 s) 2 14 /f x (3.28 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 13 /f x (1.64 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 18 /f x (52.4 ms) 0 1 0 1 0 osts0 setting prohibited stop mode release x1 pin voltage waveform a 515 chapter 23 standby function user's manual u12013ej3v2ud 23.2 standby function operations 23.2.1 halt mode (1) halt mode setting and operating status the halt mode is set by executing the halt instruction. it can be set when using either the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 23-1. halt mode operating status setting of halt mode on execution of halt instruction during main on execution of halt instruction during system clock operation subsystem clock operation without subsystem with subsystem when main system clock when main system item clock note 1 clock note 2 continues oscillation clock stops oscillation clock generator both main system and subsystem clocks can be oscillated. clock supply to the cpu stops. cpu operation stops ports (output latches) status before halt mode setting is held 16-bit timer/event counter operable operable when watch timer output is selected as count clock (f xt is selected as count clock of watch timer) or when ti00 is selected 8-bit timer/event counter operable operable when ti1 or ti2 is selected as count clock watch timer operable when f xx /2 7 is operable operable when f xt is selected as count clock selected as count clock watchdog timer operable operation stops a/d converter operable operation stops d/a converter operable real-time output port operable serial interface other than operable operable when automatic external sck is used transmit/ receive function automatic operation stops transmit/ receive function external interrupt intp0 intp0 is operable when clock supplied for peripheral hardware is selected operation stops requests as sampling clock (f xx /2 5 , f xx /2 6 , f xx /2 7 ) intp1 to intp5 operable bus line for ad0 to ad7 high impedance external a0 to a15 status before halt mode setting is held expansion astb low level wr, rd high level wait high impedance notes 1. including when an external clock is not supplied 2. including when an external clock is supplied 516 chapter 23 standby function user's manual u12013ej3v2ud (2) halt mode release the halt mode can be released by the following four types of sources. (a) release by unmasked interrupt request if an unmasked interrupt request is generated, the halt mode is released. if interrupt request acknowledgment is enabled, vectored interrupt servicing is carried out. if disabled, the next address instruction is executed. figure 23-2. halt mode release by interrupt request generation remarks 1. the broken lines indicate the case when the interrupt request which has released the standby status is acknowledged. 2. the wait time will be as follows: ? when the program branches to the vector table: 8 to 9 clocks ? when the program does not branch to the vector table: 2 to 3 clocks (b) release by non-maskable interrupt request generation if a non-maskable interrupt request is generated, the halt mode is released and vectored interrupt servicing is carried out irrespective of whether interrupt request acknowledgment is enabled or disabled. (c) release by unmasked test input if an unmasked test signal is input, the halt mode is released, and the next address instruction of the halt instruction is executed. halt instruction interrupt request wait standby release signal operating mode clock halt mode wait oscillation operating mode 517 chapter 23 standby function user's manual u12013ej3v2ud (d) release by reset input if the reset signal is input, the halt mode is released. as is the case with a normal reset operation, the program is executed after branch to the reset vector address. figure 23-3. halt mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 5.0 mhz. table 23-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt 0 0 0 next address instruction execution request 001 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 halt mode hold non-maskable interrupt interrupt servicing execution request test input 0 next address instruction execution 1 halt mode hold reset input reset processing remark : don t care halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms) 518 chapter 23 standby function user's manual u12013ej3v2ud 23.2.2 stop mode (1) stop mode setting and operating status the stop mode is set by executing the stop instruction. it can be set only when using the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait time set using the oscillation stabilization time select register (osts) elapses, the operating mode is set. the operating status in the stop mode is described below. table 23-3. stop mode operating status setting of stop mode with subsystem clock without subsystem clock item clock generator only main system clock stops oscillation cpu operation stops ports (output latches) status before stop mode setting is held 16-bit timer/event counter operable when watch timer output is operation stops selected as count clock (f xt is selected as count clock of watch timer) 8-bit timer/event counter operable when ti1 and ti2 are selected for the count clock watch timer operable when f xt is selected for the operation stops count clock watchdog timer operation stops a/d converter d/a converter operable real-time output port operable when external trigger is used or ti1 and ti2 are selected for the 8-bit timer/event counter count clock serial interface other than operable when externally supplied clock is specified as the serial clock automatic transmit/receive function and uart automatic operation stops transmit/receive function and uart external interrupt intp0 not operable requests intp1 to intp5 operable bus line for ad0 to ad7 high impedance external a0 to a15 status before stop mode setting is held expansion astb low level wr, rd high level wait high impedance 519 chapter 23 standby function user's manual u12013ej3v2ud (2) stop mode release the stop mode can be released by the following three types of sources. (a) release by unmasked interrupt request if an unmasked interrupt request is generated, the stop mode is released. if interrupt request acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. if interrupt request acknowledgment is disabled, the next address instruction is executed. figure 23-4. stop mode release by interrupt request generation remark the broken lines indicate the case when the interrupt request which has released the standby status is acknowledged. (b) release by unmasked test input if an unmasked test signal is input, the stop mode is released. after the lapse of oscillation stabilization time, the instruction at the next address of the stop instruction is executed. stop instruction interrupt request wait (time set by osts) oscillation stabilization wait status operating mode oscillation operating mode stop mode oscillation stop oscillation standby release signal clock 520 chapter 23 standby function user's manual u12013ej3v2ud (c) release by reset input if the reset signal is input, the stop mode is released and after the lapse of oscillation stabilization time, a reset operation is carried out. figure 23-5. stop mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 5.0 mhz. table 23-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt servicing execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt servicing execution 1 stop mode hold test input 0 next address instruction execution 1 stop mode hold reset input reset processing remark : don t care reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms) stop instruction oscillation 521 user's manual u12013ej3v2ud chapter 24 reset function 24.1 reset function the following two operations are available to generate a reset signal. (1) external reset input by reset pin (2) internal reset by watchdog timer program loop time detection the external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware unit is set to the status shown in table 24-1. each pin is high impedance during reset input or during the oscillation stabilization time just after reset is released. when a high level is input to the reset pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 24-2 to 24- 4 ). cautions 1. for an external reset, input a low level to the reset pin for 10 s or more. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high impedance. figure 24-1. reset function block diagram reset count clock reset controller watchdog timer stop over- flow reset signal interrupt function 522 chapter 24 reset function user's manual u12013ej3v2ud figure 24-2. reset timing by reset input figure 24-3. reset timing due to watchdog timer overflow figure 24-4. reset timing by reset input in stop mode reset internal reset signal port pin delay delay hi-z x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 normal operation watchdog timer overflow internal reset signal port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) hi-z reset internal reset signal port pin delay delay hi-z x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) stop status (oscillation stop) stop instruction execution 523 chapter 24 reset function user's manual u12013ej3v2ud table 24-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of the reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general register undefined note 2 ports (output latches) ports 0 to 3, 7, 12, 13 00h (p0 to p3, p7, p12, p13) ports 4 to 6 (p4 to p6) undefined port mode registers (pm0 to pm3, pm5 to pm7, pm12, pm13) ffh pull-up resistor option registers (puoh, puol) 00h processor clock control register (pcc) 04h oscillation mode select register (osms) 00h internal memory size switching register (ims) note 3 internal expansion ram size switching register (ixs) note 4 0ah memory expansion mode register (mm) 10h oscillation stabilization time select register (osts) 04h 16-bit timer/event counter timer register (tm0) 00h capture/compare registers (cr00, cr01) undefined clock select register (tcl0) 00h mode control register (tmc0) 00h capture/compare control register 0 (crc0) 04h output control register (toc0) 00h 8-bit timer/event counters 1 and 2 timer register (tm1, tm2) 00h compare registers (cr10, cr20) undefined clock select register (tcl1) 00h mode control registers (tmc1) 00h output control register (toc1) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. if the reset signal is input in the standby mode, the status before reset is retained even after reset. 3. the values after reset depend on the product. pd780053, 780053y: c6h, pd780054, 780054y: c8h, pd780055, 780055y: cah, pd780056, 780056y: cch, pd780058, 780058b, 780058by: cfh, pd78f0058, 78f0058y: cfh 4. provided only in the pd780058, 780058b, 780058by, 78f0058, and 78f0058y. 524 chapter 24 reset function user's manual u12013ej3v2ud table 24-1. hardware status after reset (2/2) hardware status after reset watch timer mode control register (tmc2) 00h clock select register (tcl2) 00h mode register (wdtm) 00h serial interface clock select register (tcl3) 88h shift registers (sio0, sio1) undefined mode registers (csim0, csim1, csim2) 00h serial bus interface control register (sbic) 00h slave address register (sva) undefined automatic data transmit/receive control register (adtc) 00h automatic data transmit/receive address pointer (adtp) 00h automatic data transmit/receive interval specification register (adti) 00h asynchronous serial interface mode register (asim) 00h asynchronous serial interface status register (asis) 00h baud rate generator control register (brgc) 00h serial interface pin select register (sips) 00h transmit shift register (txs) ffh receive buffer register (rxb) interrupt timing specification register (sint) 00h a/d converter mode register (adm) 01h conversion result register (adcr) undefined input select register (adis) 00h d/a converter mode register (dam) 00h conversion value setting registers (dacs0, dacs1) 00h real-time output port mode register (rtpm) 00h control register (rtpc) 00h buffer registers (rtbl, rtbh) 00h rom correction note correction address registers (corad0, corad1) 0000h correction control register (corcn) 00h interrupts request flag registers (if0l, if0h, if1l) 00h mask flag registers (mk0l, mk0h, mk1l) ffh priority specification flag registers (pr0l, pr0h, pr1l) ffh external interrupt mode registers (intm0, intm1) 00h key return mode register (krm) 02h sampling clock select register (scs) 00h note provided only in the pd780058, 780058b, 780058by, 78f0058, and 78f0058y. watchdog timer 525 user's manual u12013ej3v2ud chapter 25 rom correction 25.1 rom correction function the pd780058, 780058b, 780058by, 78f0058, 78f0058y can replace part of a program in the mask rom or flash memory with a program in the internal expansion ram. instruction bugs found in the mask rom or flash memory can be avoided, and program flow can be changed by using the rom correction function. the rom correction function can be used to correct two places (max.) of the internal rom or flash memory (program). cautions 1. rom correction can be used only for the pd780058, 780058b, 780058by, 78f0058, and 78f0058y. 2. rom correction function cannot be emulated by the in-circuit emulator (ie-78000-r, ie-78000- r-a, ie-78k0-ns, ie-78k0-ns-a, ie-78001-r-a). 25.2 rom correction configuration the rom correction function consists of the following hardware. table 25-1. rom correction configuration item configuration registers correction address registers 0, 1 (corad0, corad1) control register correction control register (corcn) figure 25-1 shows a block diagram of the rom correction function. figure 25-1. rom correction block diagram remark n = 0, 1 match corenn corstn program counter (pc) comparator correction address register (coradn) internal bus correction control register correction branch request signal (br !f7fdh) 526 chapter 25 rom correction user's manual u12013ej3v2ud (1) correction address registers 0, 1 (corad0, corad1) these registers set the start address (correction address) of the instruction(s) to be corrected in the mask rom or flash memory. the rom correction function corrects two places (max.) of the program. addresses are set to two registers, corad0 and corad1. if only one place needs to be corrected, set the address to either of the registers. corad0 and corad1 are set with a 16-bit memory manipulation instruction. reset input clears corad0 and corad1 to 0000h. figure 25-2. format of correction address registers 0 and 1 cautions 1. set corad0 and corad1 when bit 1 (coren0) and bit 3 (coren1) of the correction control register (corcn: see figure 25-3) are 0. 2. only addresses where operation codes are stored can be set to corad0 and corad1. 3. do not set the following addresses to corad0 and corad1. address value in table area of table reference instruction (callt instruction): 0040h to 007fh address value in vector table area: 0000h to 003fh (2) comparator the comparator continuously compares the correction address value set in correction address registers 0 and 1 (corad0, corad1) with the fetch address value. when bit 1 (coren0) or bit 3 (coren1) of the correction control register (corcn) is 1 and the correction address matches the fetch address value, the correction branch request signal (br !f7fdh) is generated from the rom correction circuit. ff3ah/ff3bh 0000h symbol 15 corad0 0 address ff38h/ff39h after reset 0000h r/w r/w corad1 r/w 527 chapter 25 rom correction user's manual u12013ej3v2ud 25.3 rom correction control registers the rom correction function is controlled by the correction control register (corcn). (1) correction control register (corcn) this register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. the correction control register consists of correction enable flags (coren0, coren1) and correction status flags (corst0, corst1). the correction enable flags enable or disable the comparator match detection signal, and correction status flags show that the values match. corcn is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears corcn to 00h. figure 25-3. format of correction control register note bits 0 and 2 are read-only bits. 7 0 6 0 5 0 4 0 coren1 corst1 coren0 corst0 symbol corcn address ff8ah after reset coren0 0 1 corst0 0 1 coren1 0 1 corst1 0 1 r/w r/w note 00h correction address register 0 and fetch address match detection not detected detected correction address register 0 and fetch address match detection control disabled enabled correction address register 1 and fetch address match detection not detected detected correction address register 1 and fetch address match detection control disabled enabled <3> <2> <1> <0> 528 chapter 25 rom correction user's manual u12013ej3v2ud 25.4 rom correction application (1) store the correction address and instruction after correction (patch program) to nonvolatile memory (such as eeprom tm ) outside the microcontroller. when two places should be corrected, store the branch destination judgment program as well. the branch destination judgment program checks which one of the addresses set to correction address registers 0 and 1 (corad0 or corad1) generates the correction branch. figure 25-4. example of storing to eeprom (when one place is corrected) ra78k/0 eeprom source program 00 10 0d 02 9b 02 10 00h 01h 02h ffh cseg at 1000h add a, #2 br !1002h 529 chapter 25 rom correction user's manual u12013ej3v2ud (2) assemble in advance the initialization routine as shown in figure 25-5 to correct the program. figure 25-5. initialization routine note whether the rom correction function is used or not should be judged by the port input level. for example, when the p20 input level is high, rom correction is used, otherwise, it is not used. (3) after reset, store the contents that were previously stored in the external nonvolatile memory by the user initialization routine for rom correction to internal expansion ram (see figure 25-5 ). set the start address of the instruction to be corrected to corad0 and corad1, and set bits 1 and 3 (coren0, coren1) of the correction control register (corcn) to 1. (4) set the entire-space branch instruction (br !addr16) to the specified address (f7fdh) of the internal expansion ram using the main program. (5) after the main program is started, the fetch address value and the values set in corad0 and corad1 are continuously compared by the comparator in the rom correction circuit. when these values match, the correction branch request signal is generated. simultaneously the corresponding correction status flag (corst0 or corst1) is set to 1. (6) branch to the address f7fdh via the correction branch request signal. (7) branch to the internal expansion ram address set by the main program via the entire-space branch instruction of the address f7fdh. (8) when one place is corrected, the correction program is executed. when two places are corrected, the correction status flag is checked by the branch destination judgment program, and the program branches to the correction program. no yes initialization load the contents of external nonvolatile memory into internal expansion ram correction address register setting rom correction operation enabled is rom correction used? note rom correction main program 530 chapter 25 rom correction user's manual u12013ej3v2ud figure 25-6. rom correction operation no yes internal rom (flash memory) program start does fetch address match correction address? set correction status flag correction branch (branch to address f7fdh) correction program execution rom correction 531 chapter 25 rom correction user's manual u12013ej3v2ud 25.5 rom correction usage example an example of rom correction when the instruction at address 1000h ?dd a, #1?is changed to ?dd a, #2 is shown below. figure 25-7. rom correction usage example (1) the program branches to address f7fdh when the preset value 1000h in the correction address register matches the fetch address value after the main program is started. (2) the program branches to any address (address f702h in this example) by setting the entire-space branch instruction (br !addr16) to address f7fdh by the main program. (3) the program returns to the internal rom (flash memory) program after executing the substitute instruction add a, #2. add a, #2 br !1002h br !f702h add a, #1 mov b, a 0000h 0080h program start 1000h 1002h internal rom or flash memory internal expansion ram f400h f702h f7fdh f7ffh (1) (2) (3) efffh 532 chapter 25 rom correction user's manual u12013ej3v2ud 25.6 program execution flow figures 25-8 and 25-9 show the program transition diagrams when the rom correction is used. figure 25-8. program transition diagram (when one place is corrected) (1) the program branches to address f7fdh when the fetch address matches the correction address (2) the program branches to the correction program (3) the program returns to the internal rom (flash memory) program remark shaded area: internal expansion ram jump: correction program start address correction place internal rom internal rom (flash memory) jump ffffh f7ffh f7fdh xxxxh 0000h (1) (2) (3) br !jump correction program 533 chapter 25 rom correction user's manual u12013ej3v2ud figure 25-9. program transition diagram (when two places are corrected) (1) the program branches to address f7fdh when the fetch address matches the correction address (2) the program branches to the branch destination judgment program (3) the program branches to correction program 1 via the branch destination judgment program (btclr !corst0, $xxxxh) (4) the program returns to the internal rom (flash memory) program (5) the program branches to address f7fdh when the fetch address matches the correction address (6) the program branches to the branch destination judgment program (7) the program branches to correction program 2 via the branch destination judgment program (btclr !corst1, $yyyyh) (8) the program returns to the internal rom (flash memory) program remark shaded area: internal expansion ram jump: destination judge program start address internal rom (flash memory) correction place 1 internal rom (flash memory) jump internal rom (flash memory) (1) (2) (3) (4) (5) (6) (7) (8) ffffh f7ffh f7fdh yyyyh xxxxh 0000h br !jump destination judge program correction program 2 correction program 1 correction place 2 534 chapter 25 rom correction user's manual u12013ej3v2ud 25.7 rom correction cautions (1) address values set in correction address registers 0 and 1 (corad0, corad1) must be addresses where instruction codes are stored. (2) correction address registers 0 and 1 (corad0, corad1) should be set when the correction enable flag (coren0, coren1) is 0 (when the correction branch is in the disabled state). if an address is set to corad0 or corad1 when coren0 or coren1 is 1 (when the correction branch is in the enabled state), the correction branch may start with a different address from the set address value. (3) do not set the address value of an instruction immediately after the instruction that sets the correction enable flag (coren0, coren1) to 1, to correction address register 0 or 1 (corad0, corad1); otherwise the correction branch may not start. (4) do not set the address value in the table area of the table reference instruction (callt instruction) (0040h to 007fh), and the address value in the vector table area (0000h to 003fh) to correction address registers 0 and 1 (corad0, corad1). (5) do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 (corad0, corad1). (that is, when the mapped terminal address of these instructions is n, do not set the address values of n + 1 and n + 2.) ret reti retb br $addr16 stop halt 535 user's manual u12013ej3v2ud chapter 26 pd78f0058, 78f0058y the pd78f0058 and 78f0058y have flash memory whose contents can be written, erased, rewritten with the device mounted on a pc board. table 26-1 lists the differences between the flash memory versions ( pd78f0058 and 78f0058y) and the mask rom versions ( pd780053, 780054, 780055, 780056, 780058, 780058b, 780053y, 780054y, 780055y, 780056y, and 780058by). table 26-1. differences between pd78f0058, 78f0058y and mask rom versions item pd78f0058 pd78f0058y mask rom versions pd780058 subseries pd780058y subseries internal rom structure flash memory mask rom internal rom capacity 60 kb pd780053, 780053y: 24 kb pd780054, 780054y: 32 kb pd780055, 780055y: 40 kb pd780056, 780056y: 48 kb pd780058, 780058b, 780058by: 60 kb internal expansion ram capacity 1,024 bytes pd780053, 780053y: none pd780054, 780054y: none pd780055, 780055y: none pd780056, 780056y: none pd780058, 780058b, 780058by: 1,024 bytes internal rom capacity changeable note 1 not changeable changeable/not changeable using internal memory size switching register (ims) internal expansion ram capacity changeable note 2 not changeable changeable/not changeable using interna expansion ram size switching register (ixs) supply voltage v dd = 2.7 note 3 to 5.5 v v dd = 1.8 to 5.5 v ic pin not provided provided v pp pin provided not provided p60 to p63 pin mask option not provided provided with on-chip pull-up resistors serial interface (sbi) provided not provided provided not provided serial interface (i 2 c) not provided provided not provided provided notes 1. flash memory is set to 60 kb by reset input. 2. internal expansion ram is set to 1,024 bytes by reset input. 3. v dd = 2.2 v can also be supplied. contact an nec electronics sales representative for details. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. remark only the pd780058, 780058b, 78f0058, 780058by, and 78f0058y are provided with an internal expansion ram size switching register. 536 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.1 internal memory size switching register the pd78f0058 and 78f0058y allow users to define the internal rom size using the internal memory size switching register (ims), so that the same memory mapping as that of a mask rom version with a different-size internal rom is possible. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 26-1. format of memory size switching register note when using the external device expansion function of the pd780058, 780058b, 780058by, 78f0058, and 78f0058y, set the internal rom capacity to 56 kb or less. the ims settings to give the same memory map as mask rom versions are shown in table 26-2. table 26-2. internal memory size switching register setting values target mask rom version ims setting value pd780053, 780053y c6h pd780054, 780054y c8h pd780055, 780055y cah pd780056, 780056y cch pd780058, 780058b, 780058by cfh 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h cfh after reset r/w r/w internal rom capacity selection 32 kb rom3 rom2 rom1 rom0 setting prohibited other than above internal high-speed ram capacity selection ram2 ram1 ram0 setting prohibited other than above 24 kb 1,024 bytes 110 56 kb note 40 kb 48 kb 60 kb 0110 1000 1010 1100 1110 1111 537 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.2 internal expansion ram size switching register the pd78f0058 and 78f0058y allow users to define the internal expansion ram size by using the internal expansion ram size switching register (ixs), so that the same memory mapping as that of a mask rom version with a different-size internal expansion ram is possible. ixs is set with an 8-bit memory manipulation instruction. reset input sets ixs to 0ah. figure 26-2. format of internal expansion ram size switching register the ixs settings that give the same memory map as the mask rom versions are shown in table 26-3. table 26-3. internal expansion ram size switching register setting values target mask rom version ixs setting value pd780053, 780053y 0ch pd780054, 780054y pd780055, 780055y pd780056, 780056y pd780058, 780058b, 780058by 0ah remark if a program for the pd78f0058 or 78f0058y which includes ?ov ixs, #0ch?is implemented with the pd780053, 780053y, 780054, 780054y, 780055, 780055y, 780056, or 780056y, this instruction is ignored and causes no malfunction. 7 0 symbol ixs 6 0 5 0 4 0 3 ixram3 2 ixram2 1 ixram1 0 ixram0 address fff4h 0ah after reset internal extension ram capacity selection ixram3 ixram2 ixram1 1,024 bytes 101 setting prohibited other than above ixram0 0 r/w w 0 bytes 1100 538 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.3 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the flash memory mounted on the target system (on-board). a flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products of naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontroller is solder-mounted on the target system. ? distinguishing software facilities low-quantity, varied model production ? easy data adjustment when starting mass production 26.3.1 programming environment the following shows the environment required for pd78f0058, 78f0058y flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 26-3. environment for writing program to flash memory host machine rs-232c usb dedicated flash programmer pd78f0058, pd78f0058y v pp v dd v ss reset sio/uart/port 539 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.3.2 communication mode use the communication mode shown in table 26-4 to perform communication between the dedicated flash programmer and pd78f0058, 78f0058y. table 26-4. communication mode list communication type setting note 1 pins used number mode comm port sio clock cpu flash clock multiple of v pp clock rate pulses 3-wire serial i/o sio ch-0 100 hz to optional 1 to 1.0 p27/sck0/scl 0 (3 wired, sync.) 1.25 mhz note 2 5 mhz note 2 p26/so0/sb1/sda1 p25/si0/sb0/sda0 sio ch-1 p22/sck1 1 (3 wired, sync.) p21/so1 p20/si1 sio ch-2 p72/sck2/asck 2 (3 wired, sync.) p71/so2/txd0 p70/si2/rxd0 uart (uart0) uart ch-0 4,800 to optional 1 to 1.0 p71/so2/txd0 8 (async.) 76,800 bps notes 2, 3 5 mhz note 2 p70/si2/rxd0 uart ch-1 p23/txd1 9 (async.) p24/rxd1 pseudo 3-wire port a 100 hz to optional 1 to 1.0 p32/to2 12 serial i/o (pseudo-3 wired) 1 khz 5 mhz note 2 (serial clock i/o) p31/to1 (serial data output) p30/to0 (serial data input) notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, see chapter 29 elec- trical specifications (flash memory version), chapter 30 electrical specifi- cations (flash memory version (v dd = 2.2 v) . 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. figure 26-4. communication mode selection format 10 v v pp v pp pulses flash memory write mode reset v dd v ss v dd v ss 540 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-5. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o (sio ch-0) dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd0 , v dd1 , av ref reset sck0 si0 so0 x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y (b) 3-wire serial i/o (sio ch-1) dedicated flash programmer vpp1 vdd reset sck so si gnd v pp v dd0 , v dd1 , av ref reset sck1 si1 so1 clk note x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y (c) 3-wire serial i/o (sio ch-2) dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd0 , v dd1 , av ref reset sck2 si2 so2 x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y note connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, the clk pin does not need to be connected. caution the v dd0 and v dd1 pins, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. when using the power supply connected to the v dd0 and v dd1 pins, supply voltage before starting programming. 541 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-5. example of connection with dedicated flash programmer (2/2) (d) uart (uart ch-0) dedicated flash programmer vpp1 vdd reset so (t x d) si (r x d) clk note gnd v pp v dd0 , v dd1 , av ref reset r x d0 t x d0 x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y (e) uart (uart ch-1) dedicated flash programmer vpp1 vdd reset so (t x d) si (r x d) clk note gnd v pp v dd0 , v dd1 , av ref reset r x d1 t x d1 x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y (f) pseudo 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note gnd v pp v dd0 , v dd1 , av ref reset p32 p30 p31 x1 v ss0 , v ss1 , av ss pd78f0058, 78f0058y note connect this pin when the system clock is supplied from the dedicated flash programmer. if a resonator is already connected to the x1 pin, the clk pin does not need to be connected. caution the v dd0 and v dd1 pins, if already connected to the power supply, must be connected to the vdd pin of the dedicated flash programmer. when using the power supply connected to the v dd0 and v dd1 pins, supply voltage before starting programming. 542 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud if flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv is used as a dedicated flash programmer, the following signals are generated for the pd78f0058, 78f0058y. for details, refer to the manual of flashpro iii/flashpro iv. table 26-5. pin connection list signal name i/o pin function pin name 3-wire uart pseudo 3-wire serial i/o serial i/o vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ v dd0 , v dd1 , av ref note note note voltage monitoring gnd ? ground v ss0 , v ss1 , av ss clk output clock output x1 reset output reset signal reset si (rxd) input reception signal so0/so1/so2/txd0/txd1/p31 so (txd) output transmit signal si0/si1/si2/rxd0/rxd1/p30 sck output transfer clock sck0/sck1/sck2/p32 hs input handshake signal ? note v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected. 543 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.3.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. 544 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high impedance status. figure 26-7. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd78f0058, 78f0058y (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 26-8. abnormal operation of other device pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78f0058, 78f0058y affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f0058, 78f0058y pd78f0058, 78f0058y 545 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 546 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud 26.3.4 connection of adapter for flash writing the following figures show examples of the recommended connection when the adapter for flash writing is used. figure 26-10. wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-0) pd78f0058 pd78f0058y gnd vdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vdd2 (lvdd) 547 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-11. wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-1) pd78f0058 pd78f0058y gnd vdd si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vdd2 (lvdd) 548 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-12. wiring example for flash writing adapter in 3-wire serial i/o mode (sio ch-2) pd78f0058 pd78f0058y gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 549 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-13. wiring example for flash writing adapter in uart mode (uart ch-0) pd78f0058 pd78f0058y gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 550 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-14. wiring example for flash writing adapter in uart mode (uart ch-1) pd78f0058 pd78f0058y gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 551 chapter 26 pd78f0058, 78f0058y user's manual u12013ej3v2ud figure 26-15. wiring example for flash writing adapter in pseudo 3-wire mode pd78f0058 pd78f0058y gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 552 user's manual u12013ej3v2ud chapter 27 instruction set overview this chapter describes each instruction set of the pd780058 and 780058y subseries in table form. for details of the operations and operation codes, refer to the separate document 78k/0 series instructions user? manual (u12326e) . 553 chapter 27 instruction set overview user's manual u12013ej3v2ud 27.1 conventions used in operation list 27.1.1 operand identifiers and description methods operands are described in the ?perand?column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more description methods, select one of them. uppercase letters and the symbols #, !, $ and [ ] are keywords and must be described as they are. each symbol has the following meaning. #: immediate data specification !: absolute address specification $: relative address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 27-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or label saddrp fe20h to ff1fh immediate data or label (even address only) addr16 0000h to ffffh immediate data or label (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or label addr5 0040h to 007fh immediate data or label (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, see table 5-2 special-function register list . 554 chapter 27 instruction set overview user's manual u12013ej3v2ud 27.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 27.1.3 description of flag operation column (blank): nt affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored 555 chapter 27 instruction set overview user's manual u12013ej3v2ud 27.2 operation list clocks flag note 1 note 2 zaccy 8-bit data mov r, #byte 2 4 r byte transfer saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? sfr a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed. 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 556 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy 16-bit movw rp, #word 3 6 rp word data saddrp, #word 4 8 10 (saddrp) word transfer sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 3 1 4 ax ? rp 8-bit add a, #byte 2 4 a, cy a + byte operation saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de, or hl 4. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 557 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy 8-bit sub a, #byte 2 4 a, cy a ?byte operation saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 2 4 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 + n a, cy a ?(addr16) a, [hl] 1 4 5 + n a, cy a ?(hl) a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 2 4 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 + n a, cy a ?(addr16) ?cy a, [hl] 1 4 5 + n a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) ?cy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands bytes operation instruction group 558 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy 8-bit or a, #byte 2 4 a a byte operation saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 + n a ?(addr16) a, [hl] 1 4 5 + n a ?(hl) a, [hl + byte] 2 8 9 + n a ?(hl + byte) a, [hl + b] 2 8 9 + n a ?(hl + b) a, [hl + c] 2 8 9 + n a ?(hl + c) notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed 3. except ? = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands bytes operation instruction group 559 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy 16-bit addw ax, #word 3 6 ax, cy ax + word operation subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word multiply/ mulu x 2 16 ax a x divide divuw c 2 25 ax (quotient), c (remainder) ax c increment/ inc r12 r r + 1 decrement saddr 2 4 6 (saddr) (saddr) + 1 dec r12 r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 rotate ror a, 1 1 2 (cy, a 7 a 0 , a m ?1 a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ?1 a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 3 ?0 , (hl) 7 ?4 a 3 ?0 , (hl) 3 ?0 (hl) 7 ?4 rol4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 7 ?4 , (hl) 3 ?0 a 3 ?0 , (hl) 7 ?4 (hl) 3 ?0 bcd adjba 2 4 decimal adjust accumulator after adjust addition adjbs 2 4 decimal adjust accumulator after subtract bit mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) manipu- cy, sfr.bit 3 7 cy sfr.bit lation cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 560 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy bit and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) manipu- cy, sfr.bit 3 7 cy cy sfr.bit lation cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 561 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy call/return call !addr16 3 7 (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l , pc addr16, sp sp ?2 callf !addr11 2 5 (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l , pc 15 ?11 00001, pc 10 ?0 addr11, sp sp ?2 callt [addr5] 1 6 (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk 1 6 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret 16 pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, r r r nmis 0 retb 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 stack push psw 1 2 (sp ?1) psw, sp sp ?1 manipu- rp 1 4 (sp ?1) rp h , (sp ?2) rp l , lation sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp uncondi- br !addr16 3 6 pc addr16 tional $addr16 2 6 pc pc + 2 + jdisp8 branch ax 2 8 pc h a, pc l x conditional bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 branch bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. mnemonic operands bytes operation instruction group 562 chapter 27 instruction set overview user's manual u12013ej3v2ud clocks flag note 1 note 2 zaccy condi- bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 tional sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 branch a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 b b ?1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ?, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 10 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if (saddr) 0 cpu sel rbn 2 4 rbs1, 0 n control nop 1 2 no operation ei 2 6 ie 1 (enable interrupt) di 2 6 ie 0 (disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or instruction that performs no data access is executed. 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands bytes operation instruction group 563 chapter 27 instruction set overview user's manual u12013ej3v2ud 27.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 564 chapter 27 instruction set overview user's manual u12013ej3v2ud second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a 565 chapter 27 instruction set overview user's manual u12013ej3v2ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 566 chapter 27 instruction set overview user's manual u12013ej3v2ud (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop ax !addr16 !addr11 [addr5] $addr16 567 user's manual u12013ej3v2ud chapter 28 electrical specifications (mask rom version) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +6.5 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p05, p07, p10 to p17, p20 to p27, p30 to p37, C0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref0 + 0.3 v output i oh per pin C10 ma current, high total for p01 to p05, p30 to p37, p56, p57, p60 to p67, C15 ma p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, C15 ma p50 to p55, p70 to p72, p130, p131 output i ol note per pin for other than p50 to p57, peak value 20 ma current, low p60 to p63 rms value 15 ma per pin for p50 to p57, p60 to p63 peak value 30 ma rms value 10 ma total for p50 to p55 peak value 100 ma rms value 70 ma total for p56, p57, p60 to p63 peak value 100 ma rms value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 rms value 20 ma total for p01 to p05, p30 to p37, peak value 50 ma p64 to p67, p120 to p127 rms value 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature note the rms value should be calculated as follows: [rms value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 568 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 1.0 1.0 conditions v dd = oscillation voltage range after v dd reaches oscillation voltage range min. x1 ic x2 c1 c2 x1 ic x2 c1 c2 1.0 85 v dd = 4.5 to 5.5 v v dd = 1.8 to 5.5 v x1 x2 569 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01 to p05, p10 to p17, 15 pf capacitance unmeasured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) min. 32 32 12 notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions v dd = 4.5 to 5.5 v v dd = 1.8 to 5.5 v typ. 32.768 1.2 max. 35 2 10 35 15 unit khz s khz s recommended circuit remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 ic xt2 c4 c3 r2 xt1 xt2 570 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, v dd = 1.8 to 5.5 v 0.8v dd v dd v p120 to p127, p130, p131 v ih2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8v dd v dd v p33, p34, p70, p72, reset v dd = 1.8 to 5.5 v 0.85v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7v dd 15 v (n-ch open drain) v dd = 1.8 to 5.5 v 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd ?0.5 v dd v v dd = 1.8 to 5.5 v v dd ?0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v 1.8 v v dd < 2.7 v note 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, v dd = 1.8 to 5.5 v 0 0.2v dd v p120 to p127, p130, p131 v il2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, p70, p72, reset v dd = 1.8 to 5.5 v 0 0.15v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v v dd = 1.8 to 5.5 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v 1.8 v v dd < 2.7 v note 0 0.1v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = ? ma v dd ?1.0 v high v dd = 1.8 to 5.5 v, i oh = ?00 av dd ?0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p01 to p05, p10 to p17, p20 to v dd = 4.5 to 5.5 v, 0.4 v p27, p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67, p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open drain, pulled-up (r = 1 k ? ) v ol3 i ol = 400 a 0.5 v note when p07/xt1 pin is used as p07, the inverse phase of p07 should be input to xt2 pin using an inverter. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 571 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p05, p10 to p17, p20 to p27, 3 a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 a i lih3 v in = 15 v p60 to p63 80 a input leakage i lil1 v in = 0 v p00 to p05, p10 to p17, p20 to p27, C3 a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 a i lil3 p60 to p63 C3 note a mask option pull-up r 1 v in = 0 v, p60 to p63 20 40 120 k ? resistor software pull-up r 2 v in = 0 v, p01 to p05, p10 to p17, p20 to p27, 15 30 90 k ? resistor p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 note when pull-up resistors are not connected to p60 to p63 (specified by the mask option), a low-level input leakage current of C200 a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5-clock interval, a C3 a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, high i oh per pin C1 ma total for all pins C15 ma output current, low i ol per pin for p01 to p05, p10 to p17, p20 to p27, 10 ma p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 per pin for p50 to p57, p60 to p63 15 ma total for p10 to p17, p20 to p27, p40 to p47, 10 ma p70 to p72, p130, p131 total for p01 to p05, p30 to p37, p64 to p67, 10 ma p120 to p127 total for p50 to p57, p60 to p63 70 ma remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 572 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud v dd = 5.0 v 10% note 1 3.5 7.7 ma v dd = 3.0 v 10% note 2 0.92 2.2 ma v dd = 2.0 v 10% note 2 0.47 1.2 ma v dd = 5.0 v 10% note 1 6.1 12.3 ma v dd = 3.0 v 10% note 2 1.6 3.5 ma v dd = 5.0 v 10% peripheral functions 5.5 ma operating peripheral functions 0.97 2.4 ma not operating v dd = 3.0 v 10% peripheral functions 2.1 ma operating peripheral functions 0.38 0.92 ma not operating v dd = 2.0 v 10% peripheral functions 1.1 ma operating peripheral functions 0.19 0.46 ma not operating v dd = 5.0 v 10% peripheral functions 7.5 ma operating peripheral functions 1.2 2.9 ma not operating v dd = 3.0 v 10% peripheral functions 3.3 ma operating peripheral functions 0.48 1.2 ma not operating v dd = 5.0 v 10% 46 92 a v dd = 3.0 v 10% 25 50 a v dd = 2.0 v 10% 12.5 25 a v dd = 5.0 v 10% 22.5 50 a v dd = 3.0 v 10% 3.2 13.2 a v dd = 2.0 v 10% 1.5 11.5 a v dd = 5.0 v 10% 1.0 30 a v dd = 3.0 v 10% 0.5 10 a v dd = 2.0 v 10% 0.3 10 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) i dd1 5.0 mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 3 5.0 mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 4 5.0 mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 3 i dd3 32.768 khz crystal oscillation operating mode note 6 i dd4 32.768 khz crystal oscillation halt mode note 6 i dd5 xt1 = v dd stop mode when feedback resistor is used i dd6 xt1 = v dd stop mode when feedback resistor is not used parameter symbol conditions min. typ. max. unit power supply current note 5 573 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud parameter symbol conditions min. typ. max. unit t cy operating with main system v dd = 2.7 to 5.5 v 0.8 64 s clock (f xx = 2.5 mhz) note 1 v dd = 1.8 to 5.5 v 2.0 64 s operating with main system 3.5 v v dd 5.5 v 0.4 32 s clock (f xx = 5.0 mhz) note 2 2.7 v v dd < 3.5 v 0.8 32 s operating on subsystem clock 40 note 3 122 125 s ti00 input high-/ t tih00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 4 s ti01 input high-/ t tih01 v dd = 2.7 to 5.5 v 10 s low-level width t til01 v dd = 1.8 to 5.5 v 20 s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency v dd = 1.8 to 5.5 v 0 275 khz ti1, ti2 input t tih1 v dd = 4.5 to 5.5 v 100 ns high-/low-level t til1 v dd = 1.8 to 5.5 v 1.8 s width interrupt request t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s low-level width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 4 s intp1 to intp5, p40 to p47 v dd = 2.7 to 5.5 v 10 s v dd = 1.8 to 5.5 v 20 s reset low- t rsl v dd = 2.7 to 5.5 v 10 s level width v dd = 1.8 to 5.5 v 20 s notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when external clock is used. when a crystal resonator is used, it is 114 s (min.) 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, and f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock select register (scs) (when n = 0 to 4). cycle time (minimum instruction execution time) notes 1. high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h). 2. low-speed mode operation (when the pcc is set to 04h). 3. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 4. operation with main system clock f xx = f x (when osms is set to 01h) 5. refer to the current flowing to the v dd0 and v dd1 pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 6. when the main system clock operation is stopped. ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 1.8 to 5.5 v) 574 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud t cy vs. v dd (@ f xx = f x main system clock operation) t cy vs. v dd (@ f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] cycle time t cy [ s] 575 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy ?50 ns address setup time t ads 0.85t cy ?50 ns address hold time t adh 50 ns time from address to data input t add1 (2.85 + 2n)t cy ?80 ns t add2 (4 + 2n)t cy ?100 ns time from rd to data input t rdd1 (2 + 2n)t cy ?100 ns t rdd2 (2.85 + 2n)t cy ?100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy ?60 ns t rdl2 (2.85 + 2n)t cy ?60 ns time from rd to wait input t rdwt1 0.85t cy ?50 ns t rdwt2 2t cy ?60 ns time from wr to wait input t wrwt 2t cy ?60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy ?60 ns delay time from astb to rd t astrd 25 ns delay time from astb to wr t astwr 0.85t cy + 20 ns delay time from rd to astb t rdast 0.85t cy ?10 1.15t cy + 20 ns at external fetch time from rd to address hold t rdadh 0.85t cy ?50 1.15t cy + 50 ns at external fetch time from rd to write data output t rdwd 40 ns time from wr to write data output t wrwd 050ns time from wr to address hold t wradh 0.85t cy 1.15t cy + 40 ns delay time from wait to rd t wtrd 1.15t cy + 40 3.15t cy + 40 ns delay time from wait to wr t wtwr 1.15t cy + 30 3.15t cy + 30 ns (2) read/write operation remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) 576 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud parameter symbol conditions min. max. unit astb high-level width t asth t cy ?80 ns address setup time t ads t cy ?80 ns address hold time t adh 0.4t cy ?10 ns time from address to data input t add1 (3 + 2n)t cy ?160 ns t add2 (4 + 2n)t cy ?200 ns time from rd to data input t rdd1 (1.4 + 2n)t cy ?70 ns t rdd2 (2.4 + 2n)t cy ?70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy ?20 ns t rdl2 (2.4 + 2n)t cy ?20 ns time from rd to wait input t rdwt1 t cy ?100 ns t rdwt2 2t cy ?100 ns time from wr to wait input t wrwt 2t cy ?100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy ?60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n)t cy ?20 ns delay time from astb to rd t astrd 0.4t cy ?30 ns delay time from astb to wr t astwr 1.4t cy ?30 ns delay time from rd to t rdast t cy ?10 t cy + 20 ns astb at external fetch time from rd to address t rdadh t cy ?50 t cy + 50 ns hold at external fetch time from rd to write data t rdwd 0.4t cy ?20 ns output time from wr to write data t wrwd 060ns output time from wr to address hold t wradh t cy t cy + 60 ns delay time from wait to rd t wtrd 0.6t cy + 180 2.6t cy + 180 ns delay time from wait to wr t wtwr 0.6t cy + 120 2.6t cy + 120 ns (b) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. 577 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (c) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 1.8 to 2.7 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy ?150 ns address setup time t ads t cy ?150 ns address hold time t adh 0.37t cy ?40 ns time from address to data input t add1 (3 + 2n)t cy ?320 ns t add2 (4 + 2n)t cy ?300 ns time from rd to data input t rdd1 (1.37 + 2n)t cy ?120 ns t rdd2 (2.37 + 2n)t cy ?120 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.37 + 2n)t cy ?20 ns t rdl2 (2.37 + 2n)t cy ?20 ns time from rd to wait input t rdwt1 t cy ?200 ns t rdwt2 2t cy ?200 ns time from wr to wait input t wrwt 2t cy ?200 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.37 + 2n)t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.37 + 2n)t cy ?20 ns delay time from astb to rd t astrd 0.37t cy ?50 ns delay time from astb to wr t astwr 1.37t cy ?50 ns delay time from rd to astb at t rdast t cy ?10 t cy + 20 ns external fetch time from rd to address hold t rdadh t cy ?50 t cy + 50 ns at external fetch time from rd to write data output t rdwd 0.37t cy ?40 ns time from wr to write data output t wrwd 0 120 ns time from wr to address hold t wradh t cy t cy + 120 ns delay time from wait to rd t wtrd 0.63t cy + 350 2.63t cy + 350 ns delay time from wait to wr t wtwr 0.63t cy + 240 2.63t cy + 240 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. 578 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) delay time from sck0 to so0 output (3) serial interface (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 ?50 ns v dd = 1.8 to 5.5 v t kcy1 /2 ?100 ns t sik1 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 1.8 v v dd < 2.0 v 400 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. parameter symbol conditions min. typ. max. unit t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns t sik2 2.0 v v dd 5.5 v 100 ns 1.8 v v dd < 2.0 v 150 ns t ksi2 400 ns t kso2 c = 100 pf note v dd = 2.0 to 5.5v 300 ns v dd = 1.8 to 5.5v 500 ns t r2 , t f2 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) delay time from sck0 to so0 output sck0 rise/fall time (ii) 3-wire serial i/o mode (sck0 ... external clock input) note c is the load capacitance of the so0 output line. 579 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (iv) 2-wire serial i/o mode (sck0 ... internal clock input) parameter symbol conditions min. typ. max. unit t kcy4 2.7 v v dd 5.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns t kh4 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1,300 ns 1.8 v v dd < 2.0 v 2,100 ns t kl4 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns t sik4 v dd = 2.0 to 5.5 v 100 ns v dd = 1.8 to 5.5 v 150 ns t ksi4 t kcy4 /2 ns t kso4 4.5 v v dd 5.5 v 0 300 ns 2.0 v v dd < 4.5 v 0 500 ns 1.8 v v dd < 2.0 v 0 800 ns t r4 , t f4 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function r = 1 k ? , c = 100 pf note (iii) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k ? , 2.7 v v dd 5.5 v 1,600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck0 high-level width t kh3 v dd = 2.7 to 5.5 v t kcy3 /2 ?160 ns v dd = 1.8 to 5.5 v t kcy3 /2 ?190 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2 ?50 ns v dd = 1.8 to 5.5 v t kcy3 /2 ?100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 ) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 1.8 v v dd < 2.0 v 500 ns sb0, sb1 hold time t ksi3 600 ns (from sck0 ) ns delay time from sck0 t kso3 0 300 ns to sb0, sb1 output note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) delay time from sck0 to sb0, sb1 output sck0 rise/fall time 580 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (v) sbi mode (sck0 ... internal clock output) ( pd78005x only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck0 high-/low-level t kh5 , t kl5 4.5 v v dd 5.5 v t kcy5 /2 ?50 ns width 1.8 v v dd < 4.5 v t kcy5 /2 ?150 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.0 v v dd < 4.5 v 300 ns 1.8 v v dd < 2.0 v 400 ns sb0, sb1 hold time t ksi5 t kcy5 /2 ns (from sck0 ) delay time from sck0 t kso5 r = 1 k ? , v dd = 4.5 to 5.5 v 0 250 ns to sb0, sb1 output c = 100 pf note v dd = 1.8 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy5 ns sck0 from sb0, sb1 t sbk t kcy5 ns sb0, sb1 high-level width t sbh t kcy5 ns sb0, sb1 low-level width t sbl t kcy5 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) sbi mode (sck0 ... external clock input) ( pd78005x only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck0 high-/low-level t kh6 , t kl6 4.5 v v dd 5.5 v 400 ns width 2.0 v v dd < 4.5 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns sb0, sb1 setup time t sik6 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.0 v v dd < 4.5 v 300 ns 1.8 v v dd < 2.0 v 400 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 ) delay time from sck0 t kso6 r = 1 k ? , v dd = 4.5 to 5.5 v 0 300 ns to sb0, sb1 output c = 100 pf note v dd = 1.8 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy6 ns sck0 from sb0, sb1 t sbk t kcy6 ns sb0, sb1 high-level width t sbh t kcy6 ns sb0, sb1 low-level width t sbl t kcy6 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 581 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (vii) i 2 c bus mode (scl ... internal clock output) ( pd78005xy only) parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k ? , 2.7 v v dd 5.5 v 10 s c = 100 pf note 2.0 v v dd < 2.7 v 20 s 1.8 v v dd < 2.0 v 30 s scl high-level width t kh7 v dd = 2.7 to 5.5 v t kcy7 ?160 ns v dd = 1.8 to 5.5 v t kcy7 ?190 ns scl low-level width t kl7 v dd = 4.5 to 5.5 v t kcy7 ?50 ns v dd = 1.8 to 5.5 v t kcy7 ?100 ns sda0, sda1 setup time t sik7 2.7 v v dd 5.5 v 200 ns (to scl ) 2.0 v v dd < 2.7 v 300 ns 1.8 v v dd < 2.0 v 400 ns sda0, sda1 hold time t ksi7 0ns (from scl ) delay time from scl t kso7 4.5 v v dd 5.5 v 0 300 ns to sda0, sda1 output 2.0 v v dd < 4.5 v 0 500 ns 1.8 v v dd < 2.0 v 0 600 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns v dd = 1.8 to 5.5 v 500 ns sda0, sda1 high-level width t sbh 500 ns note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. (viii) i 2 c bus mode (scl ... external clock input) ( pd78005xy only) parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1,000 ns scl high-/low-level width t kh8 ,v dd = 2.0 to 5.5 v 400 ns t kl8 v dd = 1.8 to 5.5 v 600 ns sda0, sda1 setup time t sik8 v dd = 2.0 to 5.5 v 200 ns (to scl ) v dd = 1.8 to 5.5 v 300 ns sda0, sda1 hold time t ksi8 0ns (from scl ) delay time from scl t kso8 r = 1 k ? , 4.5 v v dd 5.5 v 0 300 ns to sda0, sda1 output c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 1.8 v v dd < 2.0 v 0 600 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns v dd = 1.8 to 5.5 v 500 ns sda0, sda1 high-level width t sbh v dd = 2.0 to 5.5 v 500 ns v dd = 1.8 to 5.5 v 800 ns scl rise/fall time t r8 , when using external device expansion 160 ns t f8 function when not using external device 1 s expansion function note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. 582 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck1 high/low-level width t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 ?50 ns v dd = 1.8 to 5.5 v t kcy9 /2 ?100 ns si1 setup time (to sck1 )t sik9 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 1.8 v v dd < 2.0 v 400 ns si1 hold time (from sck1 )t ksi9 400 ns delay time from sck1 to so1 t kso9 c = 100 pf note 300 ns output (ii) 3-wire serial i/o mode (sck1 ... external clock input) note c is the load capacitance of the sck1 and so1 output lines. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck1 high/low-level width t kh10 ,t kl10 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns si1 setup time (to sck1 )t sik10 v dd = 2.0 to 5.5 v 100 ns v dd = 1.8 to 5.5 v 150 ns si1 hold time (from sck1 )t kis10 400 ns delay time from sck1 to so1 t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output v dd = 1.8 to 5.5 v 500 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 583 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck1 high-/low-level width t kh11 ,t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 ?50 ns v dd = 1.8 to 5.5 v t kcy11 /2 ?100 ns si1 setup time (to sck1 )t sik11 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 1.8 v v dd < 2.0 v 400 ns si1 hold time (from sck1 )t ksi11 400 ns delay time from sck1 to so1 t kso11 c = 100 pf note 300 ns output stb from sck1 t sbd t kcy11 /2 ?100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw 2.7 v v dd < 5.5 v t kcy11 ?30 t kcy11 + 30 ns 2.0 v < v dd < 2.7 v t kcy11 ?60 t kcy11 + 60 ns 1.8 v v dd < 2.0 v t kcy11 ?90 t kcy11 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 200 ns 1.8 v v dd < 2.0 v 300 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the sck1 and so1 output lines. 584 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1...external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck1 high-/low-level width t kh12, 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns si1 setup time (to sck1 )t sik12 v dd = 2.0 to 5.5 v 100 ns v dd = 1.8 to 5.5 v 150 ns si1 hold time (from sck1 )t ksi12 400 ns delay time from sck1 to so1 t kso12 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output v dd = 1.8 to 5.5 v 500 ns sck1 rise/fall time t r12, t f12 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 585 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2...internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck2 high-/low-level width v dd = 4.5 to 5.5 v t kcy13 /2 ?50 ns v dd = 1.8 to 5.5 v t kcy13 /2 ?100 ns si2 setup time (to sck2 ) 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 1.8 v v dd < 2.0 v 400 ns si2 hold time (from sck2 ) 400 ns delay time from sck2 to so2 c = 100 pf note 300 ns output note c is the load capacitance of the so2 output line. t kcy13 t kh13 , t kl13 t sik13 t ksi13 t kso13 (ii) 3-wire serial i/o mode (sck2...external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy14 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns sck2 high-/low-level width t kh14, 4.5 v v dd 5.5 v 400 ns t kl14 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns si2 setup time (to sck2 )t sik14 v dd = 2.0 to 5.5 v 100 ns v dd = 1.8 to 5.5 v 150 ns si2 hold time (from sck2 )t ksi14 400 ns delay time from sck2 to so2 t kso14 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output v dd = 2.0 to 5.5 v 500 ns sck2 rise/fall time t r14, other than below 160 ns t f14 v dd = 4.5 to 5.5 v 1 s when not using external device expansion function note c is the load capacitance of the so2 output line. 586 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps 2.0 v v dd < 2.7 v 19,531 bps 1.8 v v dd < 2.0 v 9,766 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy15 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 1.8 v v dd < 2.0 v 4,800 ns asck high-/low-level width t kh15, 4.5 v v dd 5.5 v 400 ns t kl15 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 1.8 v v dd < 2.0 v 2,400 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps 2.0 v v dd < 2.7 v 9,766 bps 1.8 v v dd < 2.0 v 6,510 bps asck rise/fall time t r15, v dd = 4.5 to 5.5 v, 1,000 ns t f15 when not using external device expansion function. other than above 160 ns 587 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement 588 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud interrupt request input timing reset input timing t rsl reset t intl t inth intp0 to intp5, p40 to p47 589 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address 590 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwd lower 8-bit address t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wdwr t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd lower 8-bit address 591 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud 3-wire serial i/o mode: 2-wire serial i/o mode: serial transfer timing t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 t sikm t ksim t ksom input data output data t rn t fn t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t f4 t r4 592 user's manual u12013ej3v2ud chapter 28 electrical specifications (mask rom version) sbi mode (bus release signal transfer): sbi mode (command signal transfer): i 2 c bus mode : t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t sbl t sbh t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 t sik5, 6 t kcy5,6 t kl5, 6 t kh5, 6 sck0 t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 scl sda0, sda1 t klm t sbh t sikm t ksb t ksb t khm t kcym t r8 t f8 t sikm t ksom t sbk t ksim m = 7, 8 593 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): uart mode (external clock input): t sbw t sbd t kcy11, 12 t kh11, 12 t ksi11, 12 t sik11, 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11, 12 t f12 t kso11, 12 t kcy15 t kh15 t kl15 t f15 t r15 asck note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh 594 user's manual u12013ej3v2ud chapter 28 electrical specifications (mask rom version) a/d converter characteristics ( pd780053, 780053(a), 780054, 780054(a), 780055, 780055(a), 780056, 780056(a), 780058b, 780058b(a), 780053y, 780053y(a), 780054y, 780054y(a), 780055y, 780055y(a), 780056y, 780056y(a), 780058by, 780058by(a)) (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 1.8 v av ref0 < 2.7 v 1.4 %fsr 2.7 v av ref0 5.5 v 0.6 %fsr conversion time t conv1 1.8 v av ref0 < 2.7 v 40 100 s t conv2 2.7 v av ref0 5.5 v 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 1.8 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 03 a notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. a/d converter characteristics ( pd780058) (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 0.6 %fsr conversion time t conv 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 03 a notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. caution the operating voltage range of the a/d converter and d/a converter of the pd780058 is v dd = 2.7 to 5.5 v. 595 chapter 28 electrical specifications (mask rom version) user's manual u12013ej3v2ud parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % settling time c = 30 pf note 1 av ref1 = 1.8 to 2.7 v 10 s av ref1 = 1.8 to 5.5 v 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 1.8 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? d/a converter characteristics ( pd780053, 780053(a), 780054, 780054(a), 780055, 780055(a), 780056, 780056(a), 780058b, 780058b(a), 780053y, 780053y(a), 780054y, 780054y(a), 780055y, 780055y(a), 780056y, 780056y(a), 780058by, 780058by(a)) (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % settling time c = 30 pf note 1 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 2.7 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? d/a converter characteristics ( pd780058) (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0, 1 caution the operating voltage range of the a/d converter and d/a converter of the pd780058 is v dd = 2.7 to 5.5 v. notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0, 1 596 user's manual u12013ej3v2ud chapter 28 electrical specifications (mask rom version) data memory stop mode low supply voltage data retention characteristics (ta = ?0 to +85 c) note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). parameter symbol conditions min. typ. max. unit data retention supply v dddr 1.8 5.5 v voltage data retention supply i dddr v dddr = 1.8 v 0.1 10 a current subsystem clock stop and feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr 597 user's manual u12013ej3v2ud chapter 29 electrical specifications (flash memory version) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v v pp note 1 ?.3 to +10.5 v av ref0 ?.3 to v dd + 0.3 v av ref1 ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i1 p00 to p05, p07, p10 to p17, p20 to p27, p30 to p37, ?.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain ?.3 to +16 v output voltage v o ?.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref0 + 0.3 v output i oh per pin ?0 ma current, high total for p01 to p05, p30 to p37, p56, p57, p60 to p67, ?5 ma p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, ?5 ma p50 to p55, p70 to p72, p130, p131 output i ol note 2 per pin for other than p50 to p57, peak value 20 ma current, low p60 to p63 rms value 10 ma per pin for p50 to p57, p60 to p63 peak value 30 ma rms value 15 ma total for p50 to p55 peak value 100 ma rms value 70 ma total for p56, p57, p60 to p63 peak value 100 ma rms value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 rms value 20 ma total for p01 to p05, p30 to p37, peak value 50 ma p64 to p67, p120 to p127 rms value 20 ma operating ambient t a during normal operation ?0 to +85 c temperature during flash memory programming 10 to 40 c storage t stg ?5 to +125 c temperature caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. (the note is described on the next page.) 598 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. - when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). - when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). 2. the rms value should be calculated as follows: [rms value] = [peak value] duty 2.7 v v dd 0 v 0 v v pp 2.7 v a b 599 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 1.0 1.0 conditions v dd = oscillation voltage range after v dd reaches oscillation voltage range min. 1.0 85 v dd = 4.5 to 5.5 v x1 v pp x2 c1 c2 x1 v pp x2 c1 c2 v dd = 2.7 to 5.5 v x1 x2 600 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01 to p05, p10 to p17, 15 pf capacitance unmeasured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) min. 32 32 12 notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions v dd = 4.5 to 5.5 v typ. 32.768 1.2 max. 35 2 10 35 15 unit khz s khz s cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit capacitance (t a = 25 c, v dd = v ss = 0 v) xt1 v pp xt2 c4 c3 r2 remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. v dd = 4.5 to 5.5 v xt1 xt2 601 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7 v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64-p67, p71, p120 to p127, p130, p131 v ih2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p33, p34, p70, p72, reset v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7 v dd 15 v (n-ch open drain) v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3 v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v il2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, p70, p72, reset v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = C 1 ma v dd C 1.0 v high v dd = 2.7 to 5.5 v, i oh = C 100 av dd C 0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p01 to p05, p10 to p17, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p70 to p72, p120-p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2 v dd v open drain, pulled-up (r = 1 k ? ) v ol3 i ol = 400 a 0.5 v remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 602 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p05, p10 to p17, p20 to p27, 3 a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 a i lih3 v in = 15 v p60 to p63 80 a input leakage i lil1 v in = 0 v p00 to p05, p10 to p17, p20 to p27, C 3 a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C 20 a i lil3 p60-p63 C 3 note a software pull-up r v in = 0 v, p01 to p05, p10 to p17, p20 to p27, 15 30 90 k ? resistor p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 note a low-level input leakage current of C 200 a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5-clock interval, a C 3 a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, high i oh per pin C 1ma total for all pins C 15 ma output current, low i ol per pin for p01 to p05, p10 to p17, p20 to p27, 10 ma p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 per pin for p50 to p57, p60 to p63 15 ma total for p10 to p17, p20 to p27, p40 to p47, 10 ma p70 to p72, p130, p131 total for p01 to p05, p30 to p37, p64 to p67, 10 ma p120 to p127 total for p50 to p57, p60 to p63 70 ma remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 603 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud v dd = 5.0 v 10% note 1 6.2 12.5 ma v dd = 3.0 v 10% note 2 1.3 3.1 ma v dd = 5.0 v 10% note 1 13.1 25.7 ma v dd = 3.0 v 10% note 2 2.1 4.9 ma v dd = 5.0 v 10% peripheral functions 5.6 ma operating peripheral functions 1.0 2.8 ma not operating v dd = 3.0 v 10% peripheral functions 2.9 ma operating peripheral functions 0.44 1.1 ma not operating v dd = 5.0 v 10% peripheral functions 8.4 ma operating peripheral functions 1.3 3.1 ma not operating v dd = 3.0 v 10% peripheral functions 4.5 ma operating peripheral functions 0.6 1.5 ma not operating v dd = 5.0 v 10% 110 220 a v dd = 3.0 v 10% 86 172 a v dd = 5.0 v 10% 22.5 50 a v dd = 3.0 v 10% 3.2 13.2 a v dd = 5.0 v 10% 1.0 30 a v dd = 3.0 v 10% 0.5 10 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) i dd1 note 5 5.0 mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 4 5.0 mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 3 i dd3 note 5 32.768 khz crystal oscillation operating mode note 6 i dd4 note 5 32.768 khz crystal oscillation halt mode note 6 i dd5 note 5 i dd6 note 5 xt1 = v dd stop mode when feedback resistor is not used parameter symbol conditions min. typ. max. unit power supply current 5.0 mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 3 notes 1. high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h). 2. low-speed mode operation (when pcc is set to 04h). 3. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 4. operation with main system clock f xx = f x (when osms is set to 01h) 5. refers to the current flowing to the v dd0 and v dd1 pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 6. when the main system clock operation is stopped. xt1 = v dd stop mode when feedback resistor is used 604 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with main system v dd = 2.7 to 5.5 v 0.8 64 s (min. instruction clock (f xx = 2.5 mhz) note 1 execution time) operating with main system 3.5 v v dd 5.5 v 0.4 32 s clock (f xx = 5.0 mhz) note 2 2.7 v v dd < 3.5 v 0.8 32 s operating with subsystem clock 40 note 3 122 125 s ti00 input high-/ t tih00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s ti01 input high-/ t tih01 v dd = 2.7 to 5.5 v 10 s low-level width t til01 ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency v dd = 2.7 to 5.5 v 0 275 khz ti1, ti2 input t tih1 v dd = 4.5 to 5.5 v 100 ns high-/low-level t til1 v dd = 2.7 to 5.5 v 1.8 s width interrupt request t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s low-level width intp1 to intp5, p40 to p47 v dd = 2.7 to 5.5 v 10 s reset low- t rsl v dd = 2.7 to 5.5 v 10 s level width notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when external clock is used. when a crystal resonator is used, it is 114 s (min.) 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, and f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock select register (scs) (when n = 0 to 4). 605 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud t cy vs. v dd (@ f xx = f x main system clock operation) t cy vs. v dd (@ f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] 606 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (2) read/write operation parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy ?50 ns address setup time t ads 0.85t cy ?50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy ?80 ns t add2 (4 + 2n)t cy ?100 ns data input time from rd t rdd1 (2 + 2n)t cy ?100 ns t rdd2 (2.85 + 2n)t cy ?100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy ?60 ns t rdl2 (2.85 + 2n)t cy ?60 ns wait input time from rd t rdwt1 0.85t cy ?50 ns t rdwt2 2t cy ?60 ns wait input time from wr t wrwt 2t cy ?60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy ?60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb delay time from t rdast 0.85t cy ?10 1.15t cy + 20 ns rd at external fetch address hold time from t rdadh 0.85t cy ?50 1.15t cy + 50 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr t wradh 0.85t cy 1.15t cy + 40 ns rd delay time from wait t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr delay time from wait t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) 607 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (b) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy ?80 ns address setup time t ads t cy ?80 ns address hold time t adh 0.4t cy ?10 ns data input time from address t add1 (3 + 2n)t cy ?160 ns t add2 (4 + 2n)t cy ?200 ns data input time from rd t rdd1 (1.4 + 2n)t cy ?70 ns t rdd2 (2.4 + 2n)t cy ?70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy ?20 ns t rdl2 (2.4 + 2n)t cy ?20 ns wait input time from rd t rdwt1 t cy ?100 ns t rdwt2 2t cy ?100 ns wait input time from wr t wrwt 2t cy ?100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy ?60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n)t cy ?20 ns rd delay time from astb t astrd 0.4t cy ?30 ns wr delay time from astb t astwr 1.4t cy ?30 ns astb delay time from rd t rdast t cy ?10 t cy + 20 ns at external fetch address hold time from t rdadh t cy ?50 t cy + 50 ns rd at external fetch write data output time from t rdwd 0.4t cy ?20 ns rd write data output time from t wrwd 060ns wr address hold time from wr t wradh t cy t cy + 60 ns rd delay time from wait t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr delay time from wait t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. 608 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (3) serial interface (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 ?50 ns v dd = 2.7 to 5.5 v t kcy1 /2 ?100 ns t sik1 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. parameter symbol conditions min. typ. max. unit t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns t sik2 2.7 v v dd 5.5 v 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns t r2 , t f2 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 sck0 rise/fall time (ii) 3-wire serial i/o mode (sck0 ... external clock input) note c is the load capacitance of the so0 output line. sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 609 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (iv) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit t kcy4 2.7 v v dd 5.5 v 1,600 ns t kh4 2.7 v v dd 5.5 v 650 ns t kl4 2.7 v v dd 5.5 v 800 ns t sik4 v dd = 2.7 to 5.5 v 100 ns t ksi4 t kcy4 /2 ns t kso4 4.5 v v dd 5.5 v 0 300 ns 2.7 v v dd < 4.5 v 0 500 ns t r4 , t f4 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function r = 1 k ? , c = 100 pf note (iii) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k ? , 2.7 v v dd 5.5 v 1,600 ns sck0 high-level width t kh3 c = 100 pf note v dd = 2.7 to 5.5 v t kcy3 /2 ?160 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2 ?50 ns v dd = 2.7 to 5.5 v t kcy3 /2 ?100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 ) sb0, sb1 hold time t ksi3 600 ns (from sck0 ) sb0, sb1 output delay t kso3 0 300 ns time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 sck0 rise/fall time 2.7 v v dd < 4.5 v 350 ns 610 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (v) sbi mode (sck0 ... internal clock output) ( pd78f0058 only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh5 , t kl5 4.5 v v dd 5.5 v t kcy5 /2 ?50 ns width 2.7 v v dd < 4.5 v t kcy5 /2 ?150 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.7 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi5 t kcy5 /2 ns (from sck0 ) sb0, sb1 output delay t kso5 r = 1 k ? , v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note v dd = 2.7 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy5 ns sck0 from sb0, sb1 t sbk t kcy5 ns sb0, sb1 high-level width t sbh t kcy5 ns sb0, sb1 low-level width t sbl t kcy5 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) sbi mode (sck0 ... external clock input) ( pd78f0058 only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh6 , t kl6 4.5 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.5 v 1,600 ns sb0, sb1 setup time t sik6 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.7 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 ) sb0, sb1 output delay t kso6 r = 1 k ? , v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note v dd = 2.7 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy6 ns sck0 from sb0, sb1 t sbk t kcy6 ns sb0, sb1 high-level width t sbh t kcy6 ns sb0, sb1 low-level width t sbl t kcy6 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 611 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (viii) i 2 c bus mode (scl ... external clock input) ( pd78f0058y only) (vii) i 2 c bus mode (scl ... internal clock output) ( pd78f0058y only) note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 2.7 v v dd < 5.5 v 10 s scl high-level width t kh7 2.7 v v dd < 5.5 v t kcy7 ?160 s scl low-level width t kl7 4.5 v v dd < 5.5 v t kcy7 ?50 ns 2.7 v v dd < 4.5 v t kcy7 ?100 ns sda0, sda1 setup time t sik7 2.7 v v dd < 5.5 v 200 ns (to scl ) sda0, sda1 hold time t ksi7 0ns (from scl ) sda0, sda1 output delay t kso7 4.5 v v dd < 5.5 v 0 300 ns time from scl 2.7 v v dd < 4.5 v 0 500 ns sda0, sda1 from scl t ksb 200 ns or sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k ? , c = 100 pf note parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1 s scl high-level width t kh8 400 ns sda0, sda1 setup time t sik8 200 ns (to scl ) sda0, sda1 hold time t ksi8 0ns (from scl ) sda0, sda1 output delay t kso8 4.5 v v dd < 5.5 v 0 300 ns time from scl 2.7 v v dd < 4.5 v sda0, sda1 from scl t ksb 200 ns or sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k ? , c = 100 pf note 0ns 500 612 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 ?50 ns v dd = 2.7 to 5.5 v t kcy9 /2 ?100 ns si1 setup time (to sck1 )t sik9 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si1 hold time (from sck1 )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note 300 ns (ii) 3-wire serial i/o mode (sck1 ... external clock input) note c is the load capacitance of the sck1 and so1 output lines. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh10 , t kl10 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns si1 setup time (to sck1 )t sik10 v dd = 2.7 to 5.5 v 100 ns si1 hold time (from sck1 )t kis10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 613 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh11 , t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 ?50 ns v dd = 2.7 to 5.5 v t kcy11 /2 ?100 ns si1 setup time (to sck1 )t sik11 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si1 hold time (from sck1 )t ksi11 400 ns so1 output delay time from sck1 t kso11 c = 100 pf note 300 ns stb from sck1 t sbd t kcy11 /2 ?100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw 2.7 v v dd < 5.5 v t kcy11 ?30 t kcy11 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the sck1 and so1 output lines. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck1 high-/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns si1 setup time (to sck1 )t sik12 v dd = 2.7 to 5.5 v 100 ns si1 hold time (from sck1 )t ksi12 400 ns so1 output delay time from sck1 t kso12 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck1 rise/fall time t r12 , t f12 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 614 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 ... internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy13 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck2 high-/low-level width t kh13 ,v dd = 4.5 to 5.5 v t kcy13 /2 ?50 ns t kl13 v dd = 2.7 to 5.5 v t kcy13 /2 ?100 ns si2 setup time (to sck2 )t sik13 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns si2 hold time (from sck2 )t ksi13 400 ns so2 output delay time from sck2 t kso13 c = 100 pf note 300 ns note c is the load capacitance of the so2 output line. (ii) 3-wire serial i/o mode (sck2 ... external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy14 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns sck2 high-/low-level width t kh14, 4.5 v v dd 5.5 v 400 ns t kl14 2.7 v v dd < 4.5 v 800 ns si2 setup time (to sck2 )t sik14 v dd = 2.7 to 5.5 v 100 ns si2 hold time (from sck2 )t ksi14 400 ns so2 output delay time from sck2 t kso14 c = 100 pf note v dd = 2.7 to 5.5 v 300 ns sck2 rise/fall time t r14 , other than below 160 ns t f14 v dd = 4.5 to 5.5 v 1 s when not using external device expansion function note c is the load capacitance of the so2 output line. 615 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy15 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns asck high-/low-level width t kh15 , t kl15 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps asck rise/fall time t r15 , t f15 v dd = 4.5 to 5.5 v, 1,000 ns when not using external device expansion function. other than above 160 ns 616 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement 617 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud interrupt request input timing reset input timing t rsl reset t intl t inth intp0 to intp5, p40 to p47 618 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address 619 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwd lower 8-bit address t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd lower 8-bit address 620 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud 3-wire serial i/o mode: serial transfer timing t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 t sikm t ksim t ksom input data output data t rn t fn 2-wire serial i/o mode: t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t f4 t r4 621 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud sbi mode (bus release signal transfer): sbi mode (command signal transfer): t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t sbl t sbh t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 t sik5, 6 t kcy5,6 t kl5, 6 t kh5, 6 sck0 t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 i 2 c bus mode: scl sda0, sda1 t klm t sbh m = 7, 8 t sikm t ksb t ksb t khm t kcym t sikm t ksom t sbk t ksim 622 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh t sbw t sbd t kcy11, 12 t kh11, 12 t ksi11, 12 t sik11, 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11, 12 t f12 t kso11, 12 uart mode (external clock input): t kcy15 t kh15 t kl15 t f15 t r15 asck 623 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud a/d converter characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 2.7 v av ref0 < 4.5 v 1.0 %fsr 4.5 v av ref0 5.5 v 0.6 %fsr conversion time t conv 2.7 v av ref0 5.5 v 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 03 a parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % settling time c = 30 pf note 1 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 1.8 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. d/a converter characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value set registers 0, 1 624 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage data retention power i dddr v dddr = 1.8 v 0.1 10 a supply current subsystem clock stop and feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr 625 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud flash memory programming characteristics (v dd = 2.7 to 5.5 v, t a = 10 to 40 c) (1) write/delete characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 i ddw when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 write current (v pp pin) note 1 i ppw when v pp = v pp1 5.0 mhz crystal oscillation 19.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 32.7 ma operation mode (f xx = 5.0 mhz) note 3 delete current (v dd pin) note 1 i dde when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 delete current (v pp pin) note 1 i ppe when v pp = v pp1 100 ma unit delete time t er 0.5 1 1 s total delete time t era 20 s number of overwrite c wrt delete and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 at flash memory programming 9.7 10.0 10.3 v notes 1. av ref current and port current (current flowing to internal pull-up resistor) are not included. 2. when main system clock is operating at fxx = fxx/2 (when oscillation mode select register (osms) is cleared to 00h). 3. when main system clock is operating at fxx = fxx (when osms is set to 01h). 2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 s v pp setup time from v dd t drpsr v pp high voltage 10 s reset setup time from v pp t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf 1.0 s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns 626 chapter 29 electrical specifications (flash memory version) user's manual u12013ej3v2ud flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count 627 user's manual u12013ej3v2ud chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) caution the product that can operate on v dd = 2.2 v has ?232?or later as the first 4 digits of the lot number inscribed on the package. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +6.5 v v pp note C0.3 to +10.5 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p05, p07, p10 to p17, p20 to p27, p30 to p37, C0.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref0 + 0.3 v note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (2.2 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.2 v) of the operating voltage range of v dd (see b in the figure below). 2.2 v v dd 0 v 0 v v pp 2.2 v a b if this number is 0232 or later, v dd = 2.2 v internal control code rank week code year code lot number 628 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud parameter symbol conditions ratings unit output i oh per pin C 10 ma current, high total for p01 to p05, p30 to p37, p56, p57, p60 to p67, C 15 ma p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, C 15 ma p50 to p55, p70 to p72, p130, p131 output i ol note per pin for other than p50 to p57, peak value 20 ma current, low p60 to p63 rms value 10 ma per pin for p50 to p57, p60 to p63 peak value 30 ma rms value 15 ma total for p50 to p55 peak value 100 ma rms value 70 ma total for p56, p57, p60 to p63 peak value 100 ma rms value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 rms value 20 ma total for p01 to p05, p30 to p37, peak value 50 ma p64 to p67, p120 to p127 rms value 20 ma operating ambient t a during normal operation C 40 to +85 c temperature during flash memory programming 10 to 40 c storage t stg C 65 to +125 c temperature absolute maximum ratings (t a = 25 c) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. note the rms value should be calculated as follows: [rms value] = [peak value] duty 629 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 1.0 1.0 conditions v dd = oscillation voltage range after v dd reaches oscillation voltage range min. 1.0 85 v dd = 4.5 to 5.5 v x1 v pp x2 c1 c2 x1 v pp x2 c1 c2 v dd = 2.2 to 5.5 v x1 x2 630 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01 to p05, p10 to p17, 15 pf capacitance unmeasured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) min. 32 32 12 notes 1. indicates only oscillator characteristics. see ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions v dd = 4.5 to 5.5 v typ. 32.768 1.2 max. 35 2 10 35 15 unit khz s khz s cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit capacitance (t a = 25 c, v dd = v ss = 0 v) xt1 v pp xt2 c4 c3 r2 remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. v dd = 2.2 to 5.5 v xt1 xt2 631 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7 v dd v dd v high p35 to p37, p40 to p47, v dd = 2.2 to 5.5 v 0.8 v dd v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v ih2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p33, p34, p70, p72, reset v dd = 2.2 to 5.5 v 0.85 v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7 v dd 15 v (n-ch open drain) v dd = 2.2 to 5.5 v 0.8 v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd = 2.2 to 5.5 v v dd C 0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v 2.2 v v dd < 2.7 v 0.9 v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3 v dd v low p35 to p37, p40 to p47, v dd = 2.2 to 5.5 v 0 0.2 v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v il2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2 v dd v p33, p34, p70, p72, reset v dd = 2.2 to 5.5 v 0 0.15 v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3 v dd v 2.7 v v dd < 4.5 v 0 0.2 v dd v 2.2 v v dd < 2.7 v 0 0.1 v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v v dd = 2.2 to 5.5 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2 v dd v 2.7 v v dd < 4.5 v 0 0.1 v dd v 2.2 v v dd < 2.7 v 0 0.1 v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = C 1 ma v dd C 1.0 v high v dd = 2.2 to 5.5 v, i oh = C 100 av dd C 0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p01 to p05, p10 to p17, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p70 to p72, p120-p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open drain, pulled-up (r = 1 k ? ) v ol3 i ol = 400 a 0.5 v remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 632 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud dc characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p05, p10 to p17, p20 to p27, 3 a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 a i lih3 v in = 15 v p60 to p63 80 a input leakage i lil1 v in = 0 v p00 to p05, p10 to p17, p20 to p27, C 3 a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C 20 a i lil3 p60-p63 C 3 note a software pull-up r v in = 0 v, p01 to p05, p10 to p17, p20 to p27, 15 30 90 k ? resistor p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 note a low-level input leakage current of C 200 a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5-clock interval, a C 3 a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. dc characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, high i oh per pin C 1ma total for all pins C 15 ma output current, low i ol per pin for p01 to p05, p10 to p17, p20 to p27, 10 ma p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 per pin for p50 to p57, p60 to p63 15 ma total for p10 to p17, p20 to p27, p40 to p47, 10 ma p70 to p72, p130, p131 total for p01 to p05, p30 to p37, p64 to p67, 10 ma p120 to p127 total for p50 to p57. p60 to p63 70 ma remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 633 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud v dd = 5.0 v 10% note 1 6.2 12.5 ma v dd = 3.0 v 10% note 2 1.3 3.1 ma v dd = 2.2 v note 2 0.68 1.6 ma v dd = 5.0 v 10% note 1 13.1 25.7 ma v dd = 3.0 v 10% note 2 2.1 4.9 ma v dd = 5.0 v 10% peripheral functions 5.6 ma operating peripheral functions 1.0 2.8 ma not operating v dd = 3.0 v 10% peripheral functions 2.9 ma operating peripheral functions 0.44 1.1 ma not operating v dd = 2.2 v peripheral functions 1.5 ma operating peripheral functions 0.25 0.6 ma not operating v dd = 5.0 v 10% peripheral functions 8.4 ma operating peripheral functions 1.3 3.1 ma not operating v dd = 3.0 v 10% peripheral functions 4.5 ma operating peripheral functions 0.6 1.5 ma not operating v dd = 5.0 v 10% 110 220 a v dd = 3.0 v 10% 86 172 a v dd = 2.2 v 70 140 a v dd = 5.0 v 10% 22.5 56 a v dd = 3.0 v 10% 3.2 13.2 a v dd = 2.2 v 1.5 11.5 a v dd = 5.0 v 10% 1.0 30 a v dd = 3.0 v 10% 0.5 10 a v dd = 2.2 v 0.3 10 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.2 v 0.05 10 a dc characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) 5.0 mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 4 i dd3 note 5 32.768 khz crystal oscillation operating mode note 6 i dd4 note 5 32.768 khz crystal oscillation halt mode note 6 i dd5 note 5 xt1 = v dd stop mode when feedback resistor is used i dd6 note 5 xt1 = v dd stop mode when feedback resistor is not used parameter symbol conditions min. typ. max. unit 5.0 mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 3 notes 1. high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h). 2. low-speed mode operation (when pcc is set to 04h). 3. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 4. operation with main system clock f xx = f x (when osms is set to 01h) 5. refers to the current flowing to the v dd0 and v dd1 pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 6. when the main system clock operation is stopped. power supply current i dd1 note 5 5.0 mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 3 634 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with main system v dd = 2.7 to 5.5 v 0.8 64 s (min. instruction clock (f xx = 2.5 mhz) note 1 v dd = 2.2 to 5.5 v 2.0 64 s execution time) operating with main system 3.5 v v dd 5.5 v 0.4 32 s clock (f xx = 5.0 mhz) note 2 2.7 v v dd < 3.5 v 0.8 32 s operating with subsystem clock 40 note 3 122 125 s ti00 input high-/ t tih00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s 2.2 v v dd < 2.7 v 2/f sam + 0.5 note 4 s ti01 input high-/ t tih01 v dd = 2.7 to 5.5 v 10 s low-level width t til01 v dd = 2.2 to 5.5 v 20 s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency v dd = 2.2 to 5.5 v 0 275 khz ti1, ti2 input t tih1 v dd = 4.5 to 5.5 v 100 ns high-/low-level t til1 v dd = 2.2 to 5.5 v 1.8 s width interrupt request t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s low-level width 2.2 v v dd < 2.7 v 2/f sam + 0.5 note 4 s intp1 to intp5, p40 to p47 v dd = 2.7 to 5.5 v 10 s v dd = 2.2 to 5.5 v 20 s reset low- t rsl v dd = 2.7 to 5.5 v 10 s level width v dd = 2.2 to 5.5 v 20 s notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is cleared to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when external clock is used. when a crystal resonator is used, it is 114 s (min.) 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, and f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock select register (scs) (when n = 0 to 4). 635 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud t cy vs. v dd (@ f xx = f x main system clock operation) t cy vs. v dd (@ f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] 636 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (2) read/write operation parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy ?50 ns address setup time t ads 0.85t cy ?50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy ?80 ns t add2 (4 + 2n)t cy ?100 ns data input time from rd t rdd1 (2 + 2n)t cy ?100 ns t rdd2 (2.85 + 2n)t cy ?100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy ?60 ns t rdl2 (2.85 + 2n)t cy ?60 ns wait input time from rd t rdwt1 0.85t cy ?50 ns t rdwt2 2t cy ?60 ns wait input time from wr t wrwt 2t cy ?60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n)t cy ?60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb delay time from t rdast 0.85t cy ?10 1.15t cy + 20 ns rd at external fetch address hold time from t rdadh 0.85t cy ?50 1.15t cy + 50 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr t wradh 0.85t cy 1.15t cy + 40 ns rd delay time from wait t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr delay time from wait t wtwr 1.15t cy + 30 3.15t cy + 30 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v) 637 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (b) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy ?80 ns address setup time t ads t cy ?80 ns address hold time t adh 0.4t cy ?10 ns data input time from address t add1 (3 + 2n)t cy ?160 ns t add2 (4 + 2n)t cy ?200 ns data input time from rd t rdd1 (1.4 + 2n)t cy ?70 ns t rdd2 (2.4 + 2n)t cy ?70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy ?20 ns t rdl2 (2.4 + 2n)t cy ?20 ns wait input time from rd t rdwt1 t cy ?100 ns t rdwt2 2t cy ?100 ns wait input time from wr t wrwt 2t cy ?100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy ?60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n)t cy ?20 ns rd delay time from astb t astrd 0.4t cy ?30 ns wr delay time from astb t astwr 1.4t cy ?30 ns astb delay time from rd t rdast t cy ?10 t cy + 20 ns at external fetch address hold time from t rdadh t cy ?50 t cy + 50 ns rd at external fetch write data output time from t rdwd 0.4t cy ?20 ns rd write data output time from t wrwd 060ns wr address hold time from wr t wradh t cy t cy + 60 ns rd delay time from wait t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr delay time from wait t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. 638 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (c) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy ?150 ns address setup time t ads t cy ?150 ns address hold time t adh 0.37t cy ?40 ns data input time from address t add1 (3 + 2n)t cy ?320 ns t add2 (4 + 2n)t cy ?300 ns data input time from rd t rdd1 (1.37 + 2n)t cy ?120 ns t rdd2 (2.37 + 2n)t cy ?120 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.37 + 2n)t cy ?20 ns t rdl2 (2.37 + 2n)t cy ?20 ns wait input time from rd t rdwt1 t cy ?200 ns t rdwt2 2t cy ?200 ns wait input time from wr t wrwt 2t cy ?200 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.37 + 2n)t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.37 + 2n)t cy ?20 ns rd delay time from astb t astrd 0.37t cy ?50 ns wr delay time from astb t astwr 1.37t cy ?50 ns astb delay time from rd t rdast t cy ?10 t cy + 20 ns at external fetch address hold time from t rdadh t cy ?50 t cy + 50 ns rd at external fetch write data output time from t rdwd 0.37t cy ?40 ns rd write data output time from t wrwd 0 120 ns wr address hold time from wr t wradh t cy t cy + 120 ns rd delay time from wait t wtrd 0.63t cy + 350 2.63t cy + 350 ns wr delay time from wait t wtwr 0.63t cy + 240 2.63t cy + 240 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. 639 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (3) serial interface (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 ?50 ns v dd = 2.2 to 5.5 v t kcy1 /2 ?100 ns t sik1 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.2 v v dd < 2.7 v 300 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. parameter symbol conditions min. typ. max. unit t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns t sik2 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns t r2 , t f2 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 sck0 rise/fall time (ii) 3-wire serial i/o mode (sck0 ... external clock input) note c is the load capacitance of the so0 output line. sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) so0 output delay time from sck0 640 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (iv) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol conditions min. typ. max. unit t kcy4 2.7 v v dd 5.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns t kh4 2.7 v v dd 5.5 v 650 ns 2.2 v v dd < 2.7 v 1,300 ns t kl4 2.7 v v dd 5.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns t sik4 100 ns t ksi4 t kcy4 /2 ns t kso4 4.5 v v dd 5.5 v 0 300 ns 2.2 v v dd < 4.5 v 0 500 ns t r4 , t f4 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function r = 1 k ? , c = 100 pf note (iii) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k ? , 2.7 v v dd 5.5 v 1,600 ns c = 100 pf note 2.2 v v dd < 2.7 v 3,200 ns sck0 high-level width t kh3 v dd = 2.7 to 5.5 v t kcy3 /2 ?160 ns v dd = 2.2 to 5.5 v t kcy3 /2 ?190 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2 ?50 ns v dd = 2.2 to 5.5 v t kcy3 /2 ?100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 ) 350 ns 400 ns sb0, sb1 hold time t ksi3 600 ns (from sck0 ) sb0, sb1 output delay t kso3 0 300 ns time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) sb0, sb1 output delay time from sck0 sck0 rise/fall time 2.7 v v dd < 4.5 v 2.2 v v dd < 2.7 v 641 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (v) sbi mode (sck0 ... internal clock output) ( pd78f0058, 78f0058y only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 4.5 v v dd 5.5 v 800 ns 2.2 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh5 , t kl5 4.5 v v dd 5.5 v t kcy5 /2 ?50 ns width 2.2 v v dd < 4.5 v t kcy5 /2 ?150 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.2 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi5 t kcy5 /2 ns (from sck0 ) sb0, sb1 output delay t kso5 r = 1 k ? , v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note v dd = 2.2 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy5 ns sck0 from sb0, sb1 t sbk t kcy5 ns sb0, sb1 high-level width t sbh t kcy5 ns sb0, sb1 low-level width t sbl t kcy5 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) sbi mode (sck0 ... external clock input) ( pd78f0058, 78f0058y only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 4.5 v v dd 5.5 v 800 ns 2.2 v v dd < 4.5 v 3,200 ns sck0 high-/low-level t kh6 , t kl6 4.5 v v dd 5.5 v 400 ns width 2.2 v v dd < 4.5 v 1,600 ns sb0, sb1 setup time t sik6 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.2 v v dd < 4.5 v 300 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 ) sb0, sb1 output delay t kso6 r = 1 k ? , v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note v dd = 2.2 to 5.5 v 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy6 ns sck0 from sb0, sb1 t sbk t kcy6 ns sb0, sb1 high-level width t sbh t kcy6 ns sb0, sb1 low-level width t sbl t kcy6 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. 642 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (viii) i 2 c bus mode (scl ... external clock input) ( pd78f0058y only) (vii) i 2 c bus mode (scl ... internal clock output) ( pd78f0058y only) note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines. parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 2.7 v v dd 5.5 v 10 s 2.2 v v dd < 2.7 v 20 ns scl high-level width t kh7 v dd = 2.7 to 5.5 v t kcy7 ?160 ns v dd = 2.2 to 5.5 v t kcy7 ?190 ns scl low-level width t kl7 v dd = 4.5 to 5.5 v t kcy7 ?50 ns v dd = 2.2 to 5.5 v t kcy7 ?100 ns sda0, sda1 setup time t sik7 2.7 v v dd 5.5 v 200 ns (to scl ) 2.2 v v dd < 2.7 v 300 ns sda0, sda1 hold time t ksi7 0ns (from scl ) sda0, sda1 output delay t kso7 4.5 v v dd 5.5 v 0 300 ns time from scl 2.2 v v dd < 4.5 v 0 500 ns sda0, sda1 from scl t ksb 200 ns or sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k ? , c = 100 pf note parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1 s scl high-level width t kh8 400 ns sda0, sda1 setup time t sik8 200 ns (to scl ) sda0, sda1 hold time t ksi8 0ns (from scl ) sda0, sda1 output delay t kso8 4.5 v v dd 5.5 v 0 300 ns time from scl 2.2 v v dd < 4.5 v 0 ns sda0, sda1 from scl t ksb 200 ns or sda0, sda1 from scl scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns r = 1 k ? , c = 100 pf note 500 643 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck1 high-/low-level width t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 ?50 ns v dd = 2.2 to 5.5 v t kcy9 /2 ?100 ns si1 setup time (to sck1 )t sik9 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.2 v v dd < 2.7 v 300 ns si1 hold time (from sck1 )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note 300 ns (ii) 3-wire serial i/o mode (sck1 ... external clock input) note c is the load capacitance of the sck1 and so1 output lines. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck1 high-/low-level width t kh10 , t kl10 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns si1 setup time (to sck1 )t sik10 100 ns si1 hold time (from sck1 )t kis10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note 300 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 644 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck1 high-/low-level width t kh11 , t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 ?50 ns v dd = 2.2 to 5.5 v t kcy11 /2 ?100 ns si1 setup time (to sck1 )t sik11 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.2 v v dd < 2.7 v 300 ns si1 hold time (from sck1 )t ksi11 400 ns so1 output delay time from sck1 t kso11 c = 100 pf note 300 ns stb from sck1 t sbd t kcy11 /2 ?100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw 2.7 v v dd < 5.5 v t kcy11 ?30 t kcy11 + 30 ns 2.2 v v dd < 2.7 v t kcy11 ?60 t kcy11 + 60 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns 2.2 v v dd < 2.7 v 200 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the sck1 and so1 output lines. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck1 high-/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns si1 setup time (to sck1 )t sik12 100 ns si1 hold time (from sck1 )t ksi12 400 ns so1 output delay time from sck1 t kso12 c = 100 pf note 300 ns sck1 rise/fall time t r12 , t f12 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line. 645 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 ... internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy13 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck2 high-/low-level width t kh13 ,v dd = 4.5 to 5.5 v t kcy13 /2 ?50 ns t kl13 v dd = 2.2 to 5.5 v t kcy13 /2 ?100 ns si2 setup time (to sck2 )t sik13 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.2 v v dd < 2.7 v 300 ns si2 hold time (from sck2 )t ksi13 400 ns so2 output delay time from sck2 t kso13 c = 100 pf note 300 ns note c is the load capacitance of the so2 output line. (ii) 3-wire serial i/o mode (sck2 ... external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy14 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns sck2 high-/low-level width t kh14, 4.5 v v dd 5.5 v 400 ns t kl14 2.7 v v dd < 4.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns si2 setup time (to sck2 )t sik14 100 ns si2 hold time (from sck2 )t ksi14 400 ns so2 output delay time from sck2 t kso14 c = 100 pf note 300 ns sck2 rise/fall time t r14 , other than below 160 ns t f14 v dd = 4.5 to 5.5 v 1 s when not using external device expansion function note c is the load capacitance of the so2 output line. 646 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps 2.2 v v dd < 2.7 v 19,531 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy15 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.2 v v dd < 2.7 v 3,200 ns asck high-/low-level width t kh15 , t kl15 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.2 v v dd < 2.7 v 1,600 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps 2.2 v v dd < 2.7 v 9,766 bps asck rise/fall time t r15 , t f15 v dd = 4.5 to 5.5 v, 1,000 ns when not using external device expansion function. other than above 160 ns 647 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement 648 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud interrupt request input timing reset input timing t rsl reset t intl t inth intp0 to intp5, p40 to p47 649 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address 650 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwd lower 8-bit address t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd lower 8-bit address 651 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud 3-wire serial i/o mode: serial transfer timing t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 t sikm t ksim t ksom input data output data t rn t fn 2-wire serial i/o mode: t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t f4 t r4 652 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud sbi mode (bus release signal transfer): sbi mode (command signal transfer): t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t sbl t sbh t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 t sik5, 6 t kcy5,6 t kl5, 6 t kh5, 6 sck0 t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 i 2 c bus mode: scl sda0, sda1 t klm t sbh m = 7, 8 t sikm t ksb t ksb t khm t kcym t sikm t ksom t sbk t ksim 653 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active high) 789 note 10 note 10 + n note 1 t byh t sbw t sbd t kcy11, 12 t kh11, 12 t ksi11, 12 t sik11, 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11, 12 t f12 t kso11, 12 uart mode (external clock input): t kcy15 t kh15 t kl15 t f15 t r15 asck 654 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud a/d converter characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 2.7 v av ref0 5.5 v 0.6 %fsr 2.2 v av ref0 < 2.7 v 1.4 %fsr conversion time t conv1 2.2 v av ref0 < 2.7 v 40 100 s t conv2 2.7 v av ref0 < 5.5 v 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.2 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 0 3.0 a parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % overall error note 1 av ref1 = 2.2 to 2.7 v 10 s av ref1 = 2.2 to 5.5 v 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 1.8 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. d/a converter characteristics (t a = ?0 to +85 c, v dd = 2.2 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value set registers 0, 1 c= 30 pf note 1 655 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage data retention power i dddr v dddr = 1.8 v 0.1 10 a supply current subsystem clock stop and feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr 656 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud flash memory programming characteristics (v dd = 2.7 to 5.5 v, t a = 10 to 40 c) (1) write/erase characteristics parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 i ddw when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 write current (v pp pin) note 1 i ppw when v pp = v pp1 5.0 mhz crystal oscillation 19.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 32.7 ma operation mode (f xx = 5.0 mhz) note 3 erase current (v dd pin) note 1 i dde when v pp = v pp1 5.0 mhz crystal oscillation 15.5 ma operation mode (f xx = 2.5 mhz) note 2 5.0 mhz crystal oscillation 28.7 ma operation mode (f xx = 5.0 mhz) note 3 erase current (v pp pin) note 1 i ppe when v pp = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s number of overwrites c wrt erase and write are counted as one cycle 20 times v pp power supply voltage v pp0 in normal mode 0 0.2 v dd v v pp1 during flash memory programming 9.7 10.0 10.3 v notes 1. av ref current and port current (current flowing to internal pull-up resistors) are not included. 2. when main system clock is operating at f xx = f xx /2 (when oscillation mode select register (osms) is cleared to 00h). 3. when main system clock is operating at f xx = f xx (when osms is set to 01h). 2) serial write operation characteristics parameter symbol conditions min. typ. max. unit v pp setup time t psron v pp high voltage 1.0 s v pp setup time from v dd t drpsr v pp high voltage 10 s reset setup time from v pp t psrrf v pp high voltage 1.0 s v pp count start time from reset t rfcf 1.0 s count execution time t count 2.0 ms v pp counter high-level width t ch 8.0 s v pp counter low-level width t cl 8.0 s v pp counter noise elimination width t nfw 40 ns 657 chapter 30 electrical specifications (flash memory version (v dd = 2.2 v)) user's manual u12013ej3v2ud flash write mode setting timing v dd v dd 0 v v dd reset (input) 0 v v pph v ppl v pp v pp t rfcf t psron t psrrf t drpsr t ch t cl t count 658 user's manual u12013ej3v2ud chapter 31 characteristics curves (reference values) v dd vs i dd (mask rom version, f x = 5.0 mhz, f xx = 2.5 mhz) 10 1 0.1 0.01 0.001 2 0 34567 supply voltage v dd [v] (t a = 25 c) supply current i dd [ma] pcc = 00h pcc = b0h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillating, xt1 oscillating) halt (x1 stopped, xt1 oscillating) 659 chapter 31 characteristics curves (reference values) user's manual u12013ej3v2ud v dd vs i dd (mask rom version, f x = f xx = 5.0 mhz) 10 1 0.1 0.01 0.001 2 0 34567 supply voltage v dd [v] supply current i dd [ma] pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillating, xt1 oscillating) approximately the same curve pcc = b0h halt (x1 stopped, xt1 oscillating) (t a = 25 c) 660 user's manual u12013ej3v2ud chapter 32 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h 661 chapter 32 package drawings user's manual u12013ej3v2ud 60 41 40 21 61 80 120 80-pin plastic tqfp (fine pitch) (12x12) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 14.0 0.2 12.0 0.2 1.25 14.0 0.2 c 12.0 0.2 0.10 i j h 0.22 0.05 0.5 (t.p.) k 1.0 0.2 f 1.25 m 0.145 0.05 1.0 0.05 p q n 0.10 0.1 0.05 l 0.5 0.2 s80gk-50-9eu-1 s 1.2 max. r3 + 7 ? 3 m s s n j detail of lead end c d a b r k m l p i s q g f h 662 user's manual u12013ej3v2ud chapter 33 recommended soldering conditions the pd780058 and 780058y subseries should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. table 33-1. surface mounting type soldering conditions (1/4) (1) pd780053gc- -8bt: 80-pin plastic qfp (14 14) pd780054gc- -8bt: 80-pin plastic qfp (14 14) pd780055gc- -8bt: 80-pin plastic qfp (14 14) pd780056gc- -8bt: 80-pin plastic qfp (14 14) pd780058gc- -8bt: 80-pin plastic qfp (14 14) pd780058bgc- -8bt: 80-pin plastic qfp (14 14) pd780053ygc- -8bt: 80-pin plastic qfp (14 14) pd780054ygc- -8bt: 80-pin plastic qfp (14 14) pd780055ygc- -8bt: 80-pin plastic qfp (14 14) pd780056ygc- -8bt: 80-pin plastic qfp (14 14) pd780058bygc- -8bt: 80-pin plastic qfp (14 14) pd780053gc(a)- -8bt: 80-pin plastic qfp (14 14) pd780054gc(a)- -8bt: 80-pin plastic qfp (14 14) pd780055gc(a)- -8bt: 80-pin plastic qfp (14 14) pd780056gc(a)- -8bt: 80-pin plastic qfp (14 14) pd780058bgc(a)- -8bt: 80-pin plastic qfp (14 14) pd780053ygc(a)- -8bt: 80-pin plastic qfp (14 14) pd780054ygc(a)- -8bt: 80-pin plastic qfp (14 14) pd780055ygc(a)- -8bt: 80-pin plastic qfp (14 14) pd780056ygc(a)- -8bt: 80-pin plastic qfp (14 14) pd780058bygc(a)- -8bt: 80-pin plastic qfp (14 14) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: twice or less wave soldering soldering bath temperature: 260 c or less, time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating). 663 chapter 33 recommended soldering conditions user's manual u12013ej3v2ud table 33-1. surface mounting type soldering conditions (2/4) (2) pd78f0058gc-8bt: 80-pin plastic qfp (14 14) pd78f0058ygc-8bt: 80-pin plastic qfp (14 14) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering soldering bath temperature: 260 c or less, time: 10 seconds max., ws60-107-1 count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) note after opening the dry pack, store it below 25 c and 65% rh for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 664 chapter 33 recommended soldering conditions user's manual u12013ej3v2ud table 33-1. surface mounting type soldering conditions (3/4) (3) pd780053gk- -9eu: 80-pin plastic tqfp (12 12) pd780054gk- -9eu: 80-pin plastic tqfp (12 12) pd780055gk- -9eu: 80-pin plastic tqfp (12 12) pd780056gk- -9eu: 80-pin plastic tqfp (12 12) pd780058gk- -9eu: 80-pin plastic tqfp (12 12) pd780058bgk- -9eu: 80-pin plastic tqfp (12 12) pd780053ygk- -9eu: 80-pin plastic tqfp (12 12) pd780054ygk- -9eu: 80-pin plastic tqfp (12 12) pd780055ygk- -9eu: 80-pin plastic tqfp (12 12) pd780056ygk- -9eu: 80-pin plastic tqfp (12 12) pd780058bygk- -9eu: 80-pin plastic tqfp (12 12) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) note after opening the dry pack, store it below 25 c and 65% rh for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 665 chapter 33 recommended soldering conditions user's manual u12013ej3v2ud table 33-1. surface mounting type soldering conditions (4/4) (4) pd78f0058gk-9eu: 80-pin plastic tqfp (12 12) pd78f0058ygk-9eu: 80-pin plastic tqfp (12 12) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-103-2 count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-103-2 count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) wave soldering partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) note after opening the dry pack, store it below 25 c and 65% rh for the allowable storage period. caution do not use different soldering methods together (except for partial heating). 666 user's manual u12013ej3v2ud appendix a differences between pd78054, 78058f, and 780058 subseries table a-1 shows the major differences between the pd78054, 78058f, and 780058 subseries. table a-1. major differences between pd78054, 78058f, and 780058 subseries (1/2) product name pd78054 subseries pd78058f subseries pd780058 subseries item emi noise measures none provided provided supply voltage v dd = 2.0 to 6.0 v v dd = 2.7 to 6.0 v v dd = 1.8 to 5.5 v note prom version pd78p054, 78p058 pd78p058f none flash memory version none none pd78f0058 internal rom size pd78052: 16 kb pd78056f: 48 kb pd780053: 24 kb pd78053: 24 kb pd78058f: 60 kb pd780054: 32 kb pd78054: 32 kb pd78p058f: 60 kb pd780055: 40 kb pd78p054: 32 kb pd780056: 48 kb pd78056: 48 kb pd780058b: 60 kb pd78058: 60 kb pd780058: 60 kb pd78p058: 60 kb pd78f0058: 60 kb internal high-speed ram size pd78052: 512 bytes 1,024 bytes 1,024 bytes pd78053, 78054, 78p054, 78056, 78058, 78p058: 1,024 bytes i/o ports total: 69 pins total: 68 pins ? cmos input: 2 pins ? cmos input: 2 pins ? cmos i/o: 63 pins ? cmos i/o: 62 pins ? n-ch open-drain i/o: 4 pins ? n-ch open-drain i/o: 4 pins av dd pin power supply for a/d power supply for a/d none (power supplied to port converter converter and port output output buffer is v dd0 ) buffer av ref0 pin reference voltage input to a/d converter reference voltage input and analog power supply to a/d converter caution on operation the results of the first a/d immediately after a/d conversion immediately after conversion starts the a/d conversion operation has started (cs set to 1) may not satisfy the ratings; therefore take appropriate measures such as discarding the results. serial interface channel 2 3-wire serial i/o/uart mode 3-wire serial i/o/uart mode with time division function external maskable interrupts 7 sources 6 sources emulation probe ep-78230gc-r, ep-78054gk-r np-80gc, np-80gk, ep-78230gc-r, ep-78054gk-r device file df78054 df780058 note v dd of flash memory version ( pd78f0058) = 2.7 to 5.5 v 667 appendix a differences between pd78054, 78058f, and 780058 subseries user's manual u12013ej3v2ud table a-1. major differences between pd78054, 78058f, and 780058 subseries (2/2) product name pd78054 subseries pd78058f subseries pd780058 subseries item package 80-pin plastic qfp 80-pin plastic qfp 80-pin plastic qfp (14 14) (14 14) (14 14) 80-pin plastic qfp 80-pin plastic qfp 80-pin plastic tqfp (14 14) (14 14) (fine pitch) (12 12) 80-pin ceramic wqfn 80-pin plastic tqfp (14 14) (fine pitch) (12 12) ( pd78p054, 78p058 only) ( pd78058f only) electrical specifications and refer to data sheet of individual product. see chapters 28 to 30 recommended soldering electrical conditions specifications and chapter 33 recommended soldering conditions. 668 user's manual u12013ej3v2ud appendix b development tools the following development tools are available for the development of systems which employ the pd780058, 780058y subseries. figure b-1 shows a configuration example of the tools. support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatible machines can be used for pc98- nx series computers. when using pc98-nx series computers, refer to the description for ibm pc/at compatible machines. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver. 4.0 669 appendix b development tools user's manual u12013ej3v2ud figure b-1. configuration of development tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory software package project manager (windows only) note 2 software package flash memory write environment control software embedded software real-time os i/o board performance board power supply unit 670 appendix b development tools user's manual u12013ej3v2ud b.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at compatibles windows (english version) b.2 language processing software ra78k0 assembler package cc78k0 c compiler package df780058 note 1 device file cc78k0-l note 2 c library source file notes 1. the df780058 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0-ns, id78k0, and rx78k0. 2. cc78k0-l is not included in the software package (sp78k0). this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df780058) (sold separately). 671 appendix b development tools user's manual u12013ej3v2ud remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df780058 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt b.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. 672 appendix b development tools user's manual u12013ej3v2ud b.5 debugging tools (hardware) b.5.1 when using in-circuit emulator ie-78k0-ns, ie-78k0-ns-a ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780308-ns-em1 emulation board np-80gc-tq np-h80gc-tq emulation probe tgc-080sbp conversion adapter (see figure b-2 ) np-80gc emulation probe ev-9200gc-80 conversion socket (see figure b-2 ) np-80gk emulation probe tgk-080sdw conversion adapter (see figure b-3 ) remarks 1. np-80gc, np-80gc-tq, np-h80gc-tq, and np-80gk are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgc-080sbp and tgk-080sdw are products of tokyo eletech corporation. inquiry: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to an integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this board is used for extending the ie-78k0-ns functions, and is used connected to the ie-78k0-ns. with the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. in-circuit emulator that combines the ie-78k0-ns and ie-78k0-ns-pa this adapter is used for supplying power from a 100 to 240 v ac output. this adapter is required when using a pc-9800 series computer (except notebook type) as the ie-78k0-ns host machine (c bus compatible). this is pc card and interface cable required when using a notebook-type computer as the ie-78k0-ns host machine (pcmcia socket compatible). this adapter is required when using an ibm pc/at compatible computer as the ie-78k0- ns host machine (isa bus compatible). this adapter is required when using a pc with a pci bus as the ie-78k0-ns host machine. this board emulates the operations of the peripheral hardware peculiar to a device (common to pd780308 subseries). it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for an 80-pin plastic qfp (gc-8bt type). it should be used in combination with the tgc- 080sbp. this conversion socket connects the np-80gc-tq or np-h80gc-tq to the target system board designed to mount an 80-pin plastic qfp (gc-8bt type). this probe is for an 80-pin plastic qfp (gc-8bt type) and connects an in-circuit emulator and the target system. this conversion socket connects the board of the target system created to mount an 80-pin plastic qfp (gc-8bt type) and np-80gc. this probe is for an 80-pin plastic tqfp (gk-9eu type) and connects an in-circuit emulator and the target system. this conversion adapter connects the board of the target system created to mount 80-pin plastic tqfp (gk-9eu type) and tgk-080sdw. 673 appendix b development tools user's manual u12013ej3v2ud b.5.2 when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-780308-r-em emulation board ep-78230gc-r emulation probe ev-9200gc-80 conversion socket (see figure b-2 ) ep-78054gk-r emulation probe tgk-080sdw conversion adapter (see figure b-3 ) remarks 1. tgk-080sdw is a product of tokyo eletech corporation. inquiry: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 2. the ev-9200gc-80 is sold in sets of five units. 3. the tgk-080sdw is sold in single units. this is an in-circuit emulator for debugging the hardware and software when an application system using the 78k/0 series is developed. it supports an integrated debugger (id78k0). this emulator is used with an emulation probe and interface adapter for connecting a host machine. this adapter is necessary when a pc-9800 series pc (except notebook type) is used as the host machine for the ie-78001-r-a (c bus compatible). this adapter is necessary when an ibm pc/at or compatible machine is used as the host machine for the ie-78001-r-a (isa bus compatible). this board is used with an in-circuit emulator to emulate device-specific peripheral hardware. this probe is for an 80-pin plastic qfp (gc-8bt type) and connects an in-circuit emulator and the target system. this conversion socket connects the board of the target system created to mount an 80-pin plastic qfp (gc-8bt type) and ep-78230gc-r. this probe is for an 80-pin plastic tqfp (gk-9eu type) and connects an in-circuit emulator and the target system. this conversion adapter connects the board of the target system created to mount an 80-pin plastic tqfp (gk-9eu type) and ep-78054gk-r. 674 appendix b development tools user's manual u12013ej3v2ud b.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0 series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with a device file (df780058) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns is windows-based software. (supporting in-circuit emulators it has improved c-compatible debugging functions and can display the results of ie-78k0-ns and ie-78k0-ns-a) tracing with the source program using an integrating window function that associates id78k0 the source program, disassemble display, and memory display with the trace result. integrated debugger it should be used in combination with a device file (sold separately). (supporting in-circuit emulator part number: s id78k0-ns ie-78001-r-a) s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at and compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 675 appendix b development tools user's manual u12013ej3v2ud b.7 embedded software rx78k0 the rx78k0 is a real-time os conforming to the itron specifications. real-time os a tool (configurator) for generating the nucleus of the rx78k0 and multiple information tables is supplied. used in combination with an assembler package (ra78k0) and device file (df780058) (both sold separately). 676 appendix b development tools user's manual u12013ej3v2ud b.8 system-upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have a former in-circuit emulator for 78k/0 series microcontrollers (ie-78000-r or ie-78000-r-a), that in-circuit emulator can operate as an equivalent to the ie-78001-r-a by replacing its internal break board with the ie-78001-r-bk. table b-1. system-upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit emulator owned in-circuit emulator cabinet system-up note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note for upgrading a cabinet, send your in-circuit emulator to nec electronics. 677 appendix b development tools user's manual u12013ej3v2ud b.9 drawing and footprint for conversion socket (ev-9200gc-80) figure b-2. ev-9200gc-80 drawing (for reference only) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g0 item millimeters inches a b c d e f g h i j k l m o n p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 678 appendix b development tools user's manual u12013ej3v2ud figure b-3. ev-9200gc-80 footprint (for reference only) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 based on ev-9200gc-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution 679 appendix b development tools user's manual u12013ej3v2ud b.10 drawing of conversion adapter (tgk-080sdw, tgc-080sbp) figure b-4. tgk-080sdw drawing (for reference only) (unit: mm) item millimeters inches b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.5 0.10 0.020x0.748=0.374 0.004 d 5.3 0.209 h 1.85 0.2 0.073 0.008 i 3.5 0.138 j 2.0 0.079 e 1.3 0.051 f 3.55 g 0.3 0.012 0.140 item millimeters inches b c 0.5x19=9.5 0.020x0.748=0.374 a 18.0 0.709 d h i 1.58 0.062 j 1.2 0.047 e 0.5x19=9.5 0.020x0.748=0.374 f 11.77 0.463 k 7.64 0.301 l 1.2 0.047 m q 1.2 0.047 r 1.58 0.062 s 3.55 0.140 n 1.58 0.062 o 1.2 p 7.64 0.301 0.047 w 6.8 0.268 x 8.24 0.324 y 14.8 0.583 t c 2.0 c 0.079 u 12.31 v 10.17 0.400 0.485 z 1.4 0.2 0.055 0.008 0.5 1.58 0.020 0.062 g 18.0 0.709 k 3.0 0.118 n 1.4 0.2 0.055 0.008 o 1.4 0.2 0.055 0.008 p h=1.8 1.3 h=0.071 0.051 l 0.25 m 14.0 0.551 0.010 q 0~5 0.000~0.197 11.77 0.5 0.463 0.020 tgk-080sdw-g1e t 2.4 0.094 u 2.7 0.106 v 3.9 0.154 r 5.9 s 0.8 0.031 0.232 tgk-080sdw (tqpack080sd + tqsocket080sdw) package dimension (unit: mm) e f g p r q q q o o o n ijjj lllm b c a t h d k s m2 screw u a v e c d b w x y z m f r u t v g s k j i h l n o p protrusion : 4 places q note : product by tokyo eletech corporation. 680 appendix b development tools user's manual u12013ej3v2ud item millimeters inches b 7.35 0.289 c 1.2 0.047 a (16.95) (0.667) d 1.85 0.073 e 3.5 0.138 f 2.0 g 6.0 0.236 0.079 item millimeters inches b 0.65x19=12.35 0.026x0.748=0.486 c 0.65 0.026 a 21.0 0.827 d h i c 2.0 c 0.079 14.47 0.570 j 14.95 0.589 e 12.75 0.502 f 15.15 0.596 k 13.95 0.549 l 13.7 0.539 m q 21.0 0.827 r 5.0 0.197 s n 1.15 0.045 o 12.62 p 17.52 0.690 0.497 w x y t u v z 10.35 1.15 0.407 0.045 g 17.55 0.691 reference diagram: tgc-080sbp (tqpack080sb+tqsocket080sbp) package dimension (unit: mm) note : product by tokyo eletech corporation. 1.8 0.071 4-c 1.0 4-c 0.039 7.7 0.303 4- 0.051 4- 1.3 ? 3.55 0.140 ? 5.3 0.209 ? 0.3 0.012 ? 0.9 0.035 ? h 0.25 0.010 i 13.95 j 1.025 0.040 0.549 k 1.025 0.040 l 2.4 0.094 m 2.7 0.106 tgc-080sbp-g0e cw i a b j k r u o p q h i x y z m l k j h d e g b a f g f l v m n e d protrusion height s t c figure b-5. tgc-080sbp drawing (for reference only) (unit: mm) 681 appendix b development tools user's manual u12013ej3v2ud b.11 cautions on designing target system figures b-6 to b-9 show the conditions when connecting the emulation probe to the conversion socket. follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. (1) np-80gc, np-80gc-tq, np-h80gc-tq figure b-6. distance between in-circuit emulator and conversion socket (80gc) note when np-h80gc-tq is used, the distance is 355 mm. remark np-80gc, np-80gc-tq, and np-h80gc-tq are products of naito densei machida mfg. co., ltd. tgc-080sbp is a product of tokyo eletech corporation. 155 mm note cn6 in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780308-ns-em1 conversion socket ev-9200gc-80 or conversion adapter tgc-080sbp target system emulation probe np-80gc, np-80gc-tq, np-h80gc-tq 682 appendix b development tools user's manual u12013ej3v2ud figure b-7. connection condition of target system (np-80gc-tq) remark np-80gc-tq is a product of naito densei machida mfg. co., ltd. tgc-080sbp is a product of tokyo eletech corporation. ta r g et s y stem 40 mm 23 mm 11 mm 34 mm emulation probe np-80gc-tq emulation board ie-780308-ns-em1 conversion socket tgc-080sbp 683 appendix b development tools user's manual u12013ej3v2ud (2) np-80gk, np-h80gk-tq figure b-8. distance between in-circuit emulator and conversion socket (80gk) note when np-h80gk-tq is used, the distance is 355 mm. remark np-80gk and np-h80gk-tq are products of naito densei machida mfg. co., ltd. tgk-080sdw is a product of tokyo eletech corporation. cn6 in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780308-ns-em1 conversion adapter tgk-080sdw target system 155 mm note emulation probe np-80gk, np-h80gk-tq 684 appendix b development tools user's manual u12013ej3v2ud figure b-9. connection condition of target system (np-80gk) remark np-80gk is a product of naito densei machida mfg. co., ltd. tgk-080sdw is a product of tokyo eletech corporation. 40 mm 23 mm 11 mm 34 mm ta r g et s y stem emulation probe np-80gk emulation board ie-780308-ns-em1 extension probe tgk-080sdw 685 user's manual u12013ej3v2ud appendix c register index c.1 register index (register name) 16-bit timer mode control register (tmc0) ........................................................................................................ 171 16-bit timer output control register (toc0) ....................................................................................................... 174 16-bit timer register (tm0) ............................................................................................................................... .. 168 8-bit timer mode control register (tmc1) .......................................................................................................... 216 8-bit timer output control register (toc1) ......................................................................................................... 217 8-bit timer register 1 (tm1) ............................................................................................................................... . 213 8-bit timer register 2 (tm2) ............................................................................................................................... . 213 [a] a/d conversion result register (adcr) ............................................................................................................. 256 a/d converter input select register (adis) ........................................................................................................ 260 a/d converter mode register (adm) .................................................................................................................. 258 asynchronous serial interface mode register (asim) ....................................................................................... 433 asynchronous serial interface status register (asis) ....................................................................................... 436 automatic data transmit/receive address pointer (adtp) ................................................................................ 385 automatic data transmit/receive control register (adtc) ................................................................................ 389 automatic data transmit/receive interval specification register (adti) ............................................................ 390 [b] baud rate generator control register (brgc) ................................................................................................... 437 [c] capture/compare control register 0 (crc0) ..................................................................................................... 173 capture/compare register 00 (cr00) ................................................................................................................ 167 capture/compare register 01 (cr01) ................................................................................................................ 168 compare register 10 (cr10) ............................................................................................................................. 21 3 compare register 20 (cr20) ............................................................................................................................. 21 3 correction address register 0 (corad0) ......................................................................................................... 526 correction address register 1 (corad1) ......................................................................................................... 526 correction control register (corcn) ................................................................................................................ 527 [d] d/a conversion value set register 0 (dacs0) .................................................................................................. 277 d/a conversion value set register 1 (dacs1) .................................................................................................. 277 d/a converter mode register (dam) .................................................................................................................. 278 [e] external interrupt mode register 0 (intm0) ............................................................................................. 177, 483 external interrupt mode register 1 (intm1) ............................................................................................. 261, 483 [i] internal expansion ram size switching register (ixs) ..................................................................................... 537 internal memory size switching register (ims) ........................................................................................ 506, 536 686 appendix c register index user's manual u12013ej3v2ud interrupt mask flag register 0h (mk0h) ............................................................................................................ 481 interrupt mask flag register 0l (mk0l) ............................................................................................................. 481 interrupt mask flag register 1l (mk1l) .................................................................................................... 481, 499 interrupt request flag register 0h (if0h) ........................................................................................................... 480 interrupt request flag register 0l (if0l) ............................................................................................................ 480 interrupt request flag register 1l (if1l) ................................................................................................... 480, 499 interrupt timing specification register (sint) ........................................................................................... 294, 345 [k] key return mode register (krm) .............................................................................................................. 143, 500 [m] memory expansion mode register (mm) .................................................................................................. 142, 505 [o] oscillation mode select register (osms) .......................................................................................................... 151 oscillation stabilization time select register (osts) ........................................................................................ 514 [p] port 0 (p0) ............................................................................................................................... .......................... 122 port 1 (p1) ............................................................................................................................... .......................... 124 port 12 (p12) ............................................................................................................................... ....................... 136 port 13 (p13) ............................................................................................................................... ....................... 137 port 2 (p2) ............................................................................................................................... ................. 125, 127 port 3 (p3) ............................................................................................................................... .......................... 129 port 4 (p4) ............................................................................................................................... .......................... 130 port 5 (p5) ............................................................................................................................... .......................... 131 port 6 (p6) ............................................................................................................................... .......................... 132 port 7 (p7) ............................................................................................................................... .......................... 134 port mode register 0 (pm0) ............................................................................................................................... 138 port mode register 1 (pm1) ............................................................................................................................... 138 port mode register 12 (pm12) .................................................................................................................. 138, 472 port mode register 13 (pm13) ........................................................................................................................... 138 port mode register 2 (pm2) ............................................................................................................................... 138 port mode register 3 (pm3) ............................................................................................. 138, 176, 218, 249, 253 port mode register 5 (pm5) ............................................................................................................................... 138 port mode register 6 (pm6) ............................................................................................................................... 138 port mode register 7 (pm7) ............................................................................................................................... 138 priority specify flag register 0h (pr0h) ............................................................................................................ 482 priority specify flag register 0l (pr0l) ............................................................................................................. 482 priority specify flag register 1l (pr1l) ............................................................................................................. 482 processor clock control register (pcc) ............................................................................................................. 148 program status word (psw) ....................................................................................................................... 96, 487 pull-up resistor option register h (puoh) ........................................................................................................ 141 pull-up resistor option register l (puol) .......................................................................................................... 141 687 appendix c register index user's manual u12013ej3v2ud [r] real-time output buffer register h (rtbh) ....................................................................................................... 471 real-time output buffer register l (rtbl) ........................................................................................................ 471 real-time output port control register (rtpc) .................................................................................................. 473 real-time output port mode register (rtpm) ................................................................................................... 472 receive buffer register (rxb) ........................................................................................................................... 431 receive shift register (rxs) .............................................................................................................................. 4 31 [s] sampling clock select register (scs) ....................................................................................................... 178, 485 serial bus interface control register (sbic) ............................................................................................. 293, 343 serial i/o shift register 0 (sio0) ............................................................................................................... 286, 338 serial i/o shift register 1 (sio1) ........................................................................................................................ 385 serial interface pin select register (sips) ......................................................................................................... 441 serial operating mode register 0 (csim0) ............................................................................................... 290, 342 serial operating mode register 1 (csim1) ........................................................................................................ 388 serial operating mode register 2 (csim2) ........................................................................................................ 432 slave address register (sva) ................................................................................................................... 286, 338 [t] timer clock select register 0 (tcl0) ........................................................................................................ 169, 247 timer clock select register 1 (tcl1) ................................................................................................................. 214 timer clock select register 2 (tcl2) ................................................................................................ 233, 241, 251 timer clock select register 3 (tcl3) ................................................................................................ 288, 340, 386 transmit shift register (txs) ............................................................................................................................. 43 1 [w] watch timer mode control register (tmc2) ...................................................................................................... 236 watchdog timer mode register (wdtm) ........................................................................................................... 243 688 appendix c register index user's manual u12013ej3v2ud c.2 register index (symbol) [a] adcr: a/d conversion result register ........................................................................................................ 256 adis: a/d converter input select register ................................................................................................. 260 adm: a/d converter mode register .......................................................................................................... 258 adtc: automatic data transmit/receive control register ........................................................................... 389 adti: automatic data transmit/receive interval specification register .................................................... 390 adtp: automatic data transmit/receive address pointer .......................................................................... 385 asim: asynchronous serial interface mode register ................................................................................ 433 asis: asynchronous serial interface status register ............................................................................... 436 [b] brgc: baud rate generator control register .............................................................................................. 437 [c] corad0: correction address register 0 ......................................................................................................... 526 corad1: correction address register 1 ......................................................................................................... 526 corcn: correction control register .............................................................................................................. 527 cr00: capture/compare register 00 .......................................................................................................... 167 cr01: capture/compare register 01 .......................................................................................................... 168 cr10: compare register 10 ....................................................................................................................... 213 cr20: compare register 20 ....................................................................................................................... 213 crc0: capture/compare control register 0 ............................................................................................... 173 csim0: serial operating mode register 0 ........................................................................................... 290, 342 csim1: serial operating mode register 1 .................................................................................................... 388 csim2: serial operating mode register 2 .................................................................................................... 432 [d] dacs0: d/a conversion value set register 0 ............................................................................................... 277 dacs1: d/a conversion value set register 1 ............................................................................................... 277 dam: d/a converter mode register .......................................................................................................... 278 [i] if0h: interrupt request flag register 0h ................................................................................................... 480 if0l: interrupt request flag register 0l .................................................................................................... 480 if1l: interrupt request flag register 1l ........................................................................................... 480, 499 ims: internal memory size switching register ............................................................................... 506, 536 intm0: external interrupt mode register 0 ........................................................................................ 177, 483 intm1: external interrupt mode register 1 ........................................................................................ 261, 483 ixs: internal expansion ram size switching register ............................................................................ 537 [k] krm: key return mode register ....................................................................................................... 143, 500 [m] mk0h: interrupt mask flag register 0h ....................................................................................................... 481 mk0l: interrupt mask flag register 0l ....................................................................................................... 481 689 appendix c register index user's manual u12013ej3v2ud mk1l: interrupt mask flag register 1l .............................................................................................. 481, 499 mm: memory expansion mode register ......................................................................................... 142, 505 [o] osms: oscillation mode selection register ................................................................................................ 151 osts: oscillation stabilization time select register ................................................................................... 514 [p] p0: port 0 ............................................................................................................................... ................ 122 p1: port 1 ............................................................................................................................... ................ 124 p12: port 12 ............................................................................................................................... .............. 136 p13: port 13 ............................................................................................................................... .............. 137 p2: port 2 ............................................................................................................................... ....... 125, 127 p3: port 3 ............................................................................................................................... ................ 129 p4: port 4 ............................................................................................................................... ................ 130 p5: port 5 ............................................................................................................................... ................ 131 p6: port 6 ............................................................................................................................... ................ 132 p7: port 7 ............................................................................................................................... ................ 134 pcc: processor clock control register ..................................................................................................... 148 pm0: port mode register 0 ....................................................................................................................... 138 pm1: port mode register 1 ....................................................................................................................... 138 pm12: port mode register 12 ............................................................................................................ 138, 472 pm13: port mode register 13 ..................................................................................................................... 138 pm2: port mode register 2 ....................................................................................................................... 138 pm3: port mode register 3 ..................................................................................... 138, 176, 218, 249, 253 pm5: port mode register 5 ....................................................................................................................... 138 pm6: port mode register 6 ....................................................................................................................... 138 pm7: port mode register 7 ....................................................................................................................... 138 pr0h: priority specification flag register 0h ............................................................................................. 482 pr0l: priority specification flag register 0l .............................................................................................. 482 pr1l: priority specification flag register 1l .............................................................................................. 482 psw: program status word ................................................................................................................ 96, 487 puoh: pull-up resistor option register h ................................................................................................... 141 puol: pull-up resistor option register l .................................................................................................... 141 [r] rtbh: real-time output buffer register h .................................................................................................. 471 rtbl: real-time output buffer register l .................................................................................................. 471 rtpc: real-time output port control register ............................................................................................ 473 rtpm: real-time output port mode register .............................................................................................. 472 rxb: receive buffer register .................................................................................................................... 431 rxs: receive shift register ...................................................................................................................... 431 [s] sbic: serial bus interface control register ...................................................................................... 293, 343 scs: sampling clock select register ............................................................................................... 178, 485 sfr: special-function register ................................................................................................................. 115 sint: interrupt timing specification register .................................................................................... 294, 345 690 appendix c register index user's manual u12013ej3v2ud sio0: serial i/o shift register 0 ........................................................................................................ 286, 338 sio1: serial i/o shift register 1 ................................................................................................................. 385 sips: serial interface pin select register .................................................................................................. 441 sva: slave address register ........................................................................................................... 286, 338 [t] tcl0: timer clock select register 0 ................................................................................................. 169, 247 tcl1: timer clock select register 1 .......................................................................................................... 214 tcl2: timer clock select register 2 ......................................................................................... 233, 241, 251 tcl3: timer clock select register 3 ......................................................................................... 288, 340, 386 tm0: 16-bit timer register ......................................................................................................................... 168 tm1: 8-bit timer register 1 ........................................................................................................................ 213 tm2: 8-bit timer register 2 ........................................................................................................................ 213 tmc0: 16-bit timer mode control register .................................................................................................. 171 tmc1: 8-bit timer mode control register .................................................................................................... 216 tmc2: watch timer mode control register ................................................................................................. 236 toc0: 16-bit timer output control register ................................................................................................. 174 toc1: 8-bit timer output control register ................................................................................................... 217 txs: transmit shift register ..................................................................................................................... 431 [w] wdtm: watchdog timer mode register ....................................................................................................... 243 691 user's manual u12013ej3v2ud appendix d revision history the revision history of this edition is listed in the table below. ?hapter?indicates the chapter of the previous edition where the revision was made. edition revisions chapter 2nd change of following block diagrams of ports: chapter 6 port functions edition figures 6-5 and 6-7 p20, p21, and p23 to p26 block diagram , figures 6-6 and 6-8 p22 and p27 block diagram , figure 6-9 p30 to p37 block diagram , and figure 6-16 p71 and p72 block diagram addition of table 7-2 relationships between cpu clock and chapter 7 clock generator minimum instruction execution time addition of figures 9-10 and 9-13 square wave output chapter 9 8-bit timer/event counter operation timing addition of (7) conversion result immediately after a/d chapter 14 a/d converter converter start to 14.5 how to read the a/d converter characteristics table correction of note on bsye in figure 16-5 serial bus chapter 16 serial interface interface control register format channel 0 ( pd780058 subseries) addition of caution to 16.4.3 (2) (a) bus release signal (rel) and (b) command signal (cmd) addition of (3) msb/lsb switching as the start bit to 18.4.2 chapter 18 serial interface 3-wire serial i/o mode operation channel 1 change of 18.4.3 (3) (d) busy control option, (e) busy & strobe control option , and (f) bit slippage detection function in old edition to (4) synchronization control , and improvement of explanation correction of figure 19-11 receive error timing chapter 19 serial interface addition of (3) msb/lsb switching as the start bit to 19.4.3 channel 2 3-wire serial i/o mode addition of 19.4.4 restrictions in uart mode addition of note to 26.1 memory size switching register chapter 26 pd78f0058, 78f0058y 26.3 flash memory programming change of product name of flash programmer from flashpro to flashpro ii addition of appendix a differences among pd78054, appendix a differences among 78058f, and 780058 subseries pd78054, 78058f, and 780058 subseries total revision: support of in-circuit emulators ie-78k0-ns and appendix b development tools ie-78001-r-a total revision: deletion of fuzzy inference development support appendix c embedded software system appendix d revision history 692 user's manual u12013ej3v2ud edition revisions chapter 3rd edition deletion of following product throughout pd780058y addition of following products pd780058b, 780058by, 780053(a), 780053y(a), 780054(a), 780054y(a), 780055(a), 780055y(a), 780056(a), 780056y(a), 780058b(a), 780058by(a) deletion of following packages 80-pin plastic qfp (gc-3b9 type) 80-pin plastic tqfp (gk-be9 type) addition of following package 80-pin plastic tqfp (gk-9eu type) 1.1 features, 1.7 outline of functions chapter 1 outline change of operating voltage range of a/d and d/a converters of ( pd780058 subseries) pd780058 and 78f0058 change of supply voltage of pd78f0058 addition of 1.9 differences between standard model and (a) model 2.1 features, 2.7 outline of functions chapter 2 outline change of operating voltage range of a/d and d/a converters of ( pd780058y subseries) pd78f0058y change of supply voltage of pd78f0058y addition of 2.9 differences between standard model and (a) model change of processing when a/d converter is not used in 3.2.11 av ref0 chapter 3 pin functions change of recommended connection of unused pins and connection of p60 ( pd780058 subseries) to p63, av ref1 , and v pp pins in table 3-1 pin i/o circuit types change of processing when a/d converter is not used in 4.2.11 av ref0 chapter 4 pin functions change of recommended connection of unused pins and connection of p60 ( pd780058y subseries) to p63, av ref1 , and v pp pins in table 4-1 pin i/o circuit types modification of note 2 in 6.2.8 port 6 chapter 6 port functions addition of note on feedback resistor to figure 7-3 format of processor chapter 7 clock clock control register generator addition of table 8-5 intp1/ti01 pin valid edge and cr00 capture chapter 8 16-bit trigger valid edge timer/event counter addition of table 8-6 intp0/ti00 pin valid edge and cr01 capture trigger valid edge correction of note on valid edge of intp0/ti00/p00 and intp1/ti01/p01 pin in figure 8-8 format of external interrupt mode register 0 addition of figure 8-17 configuration of ppg output addition of figure 8-18 ppg output operation timing 8.5 16-bit timer/event counter operating cautions addition of description on ti01/p01/intp1 to (5) valid edge setting addition of (c) one-shot pulse output function to (6) re-trigger of one-shot pulse addition of (8) conflict operation addition of (9) timer operation addition of (10) capture operation addition of (11) compare operation addition of (12) edge detection modification of note on changing count clock in figure 10-2 format of chapter 10 watch timer timer clock select register 2 appendix d revision history 693 user's manual u12013ej3v2ud edition revisions chapter 3rd edition modification of note on changing count clock in figure 11-2 format of chapter 11 watchdog timer clock select register 2 timer addition of note on rewriting tcl2 in figure 13-2 format of timer clock chapter 13 buzzer select register 2 output controller modification of figure 14-5 a/d converter basic operation chapter 14 a/d addition of table 14-2 a/d conversion sampling time and a/d converter converter start delay time addition of 14.5 how to read a/d converter characteristics table 14.6 a/d converter cautions change of description in (1) power consumption in standby mode addition of (3) conflicting operations addition of (6) input impedance of ani0 to ani7 pins addition of (10) timing at which a/d conversion result is undefined addition of (11) notes on board design addition of (12) av ref0 pin addition of (13) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance addition of description of processing when d/a converter is not used in chapter 15 d/a 15.5 d/a converter cautions (3) av ref1 pin converter addition of 17.4.7 restrictions in i 2 c bus mode 2 chapter 17 serial interface channel 0 ( pd780058y subseries) addition of 19.4.5 restrictions in uart mode 2 chapter 19 serial interface channel 2 addition of caution when interrupt is acknowledged to figure 21-2 format chapter 21 interrupt of interrupt request flag register and test functions addition of description on ti01/p01/intp1 pin to figure 21-5 format of external interrupt mode register 0 addition of caution to 25.1 rom correction function chapter 25 rom correction modification of table 26-1 differences between pd78f0058, 78f0058y chapter 26 pd78f0058, and mask rom versions 78f0058y total revision of description on flash memory programming as 26.3 flash memory characteristics addition of chapter 28 electrical specifications (mask rom chapter 28 electrical version) specifications (mask rom version) addition of chapter 29 electrical specifications (flash chapter 29 electrical memory version) specifications (flash memory version) addition of chapter 30 electrical specifications (flash chapter 30 electrical memory version (v dd = 2.2 v)) specifications (flash memory version (v dd = 2.2 v)) addition of chapter 31 characteristics curves (reference chapter 31 values) characteristics curves (reference values) addition of chapter 32 package drawings chapter 32 package drawings appendix d revision history 694 user's manual u12013ej3v2ud edition revisions chapter 3rd edition addition of chapter 33 recommended soldering conditions chapter 33 recommended soldering conditions correction of appendix a differences between pd78054, 78058f, appendix a differences and 780058 between pd78054, 78058f, and 780058 subseries total revision of appendix b development tools appendix b development transfer of description of embedded software to appendix b tools development tools |
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